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參數(shù)資料
| 型號： | HT86R384 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Voice Synthesizer 8-Bit OTP MCU |
| 中文描述： | 語音合成器8位微控制器檢察官辦公室 |
| 文件頁數(shù)： | 15/41頁 |
| 文件大小： | 286K |
| 代理商： | HT86R384 |
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HT86R384
Rev. 0.10
15
May 18, 2007
Preliminary
by OTPoption. If the Watchdog Timer is disabled, all the
executions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with pe-
riod 78 s normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20 ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
If WS2, WS1, WS0 all equal to 1, the division ratio is up to
1:128, and the maximum time-out period is 2.6 seconds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . Whereas in
the HALT mode, the overflow will initialize a warm re -
set only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instruc-
tions, or a HALT instruction. The software instruction
is CLR WDT and execution of the CLR WDT instruc-
tion will clear the WDT.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
Power Down
HALT
The HALT mode is initialized by a HALT instruction and
results in the following:
The system oscillator will be turned off but the WDT os-
cillatorkeepsrunning(iftheWDToscillatorisselected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and recount
again.
All I/O ports maintain their their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDToverflow per-
forms a warm reset . By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the CLR WDT instruction, and is set when
the HALT instructionisexecuted.TheTOflagissetifa
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP. The other maintain
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by a OTP option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two se-
quences may happen. If the related interrupt is disabled
or the interrupt is enabled by the stack is full, the pro-
gram will resume execution at the next instruction. If the
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
Onceawake-upeventoccurs,ittakes1024systemclock
period to resume normal operation. In other words, a
dummy cycle period will be inserted after a wake-up. If
the wake-up results from an interrupt acknowledge, the
actual interrupt subroutine will be delayed by one more
cycle. If the wake-up results in next instruction execution,
this will be executed immediately after a dummy period is
finished.Ifaninterruptrequestflagissetto 1 beforeen-
tering the HALT mode, the wake-up function of the re-
lated interrupt will be disabled. To minimize power
consumption, all I/O pins should be carefully managed
before entering the HALT status.
Reset
There are 3 ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during any other reset
conditions. Most registers are reset to their initial condi-
tion when the reset conditions are met. By examining
the PDF flag and TO flag, the program can distinguish
between different chip resets .
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
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