HT86R384
Rev. 0.10
18
May 18, 2007
Preliminary
Timer Counter 2
The timer counter TMR2 is also a 16-bit programmable
count-up counter. It operates in the same manner as
Timer/Event Counter 0/1, but the clock source of TMR2
is from only internal instruction cycle (T1). Therefore
only (TM1,TM0)=(1,0) is allowable.
Timer Counter 3 (RTC Time Base)
The timer counter TMR3 is an 8-bit programmable
count-up counter. Its counting is as the same manner as
Timer Event Counter 0/1 and Timer Counter 2, but the
clock source of TMR3 can be from internal instruction
cycle (T1) or external 32kHz crystal which is connected
to XIN and XOUT. The TMR3 s clock source is deter-
mined by OTP option. If the 32kHz crystal is enabled,
then TMR3 s clock source is 32kHz which is from XIN
and XOUT. If the 32kHz crystal is disabled, then TMR3 s
clock source is internal T1.
The TMR3 is internal clock source only, i.e.
(TM1,TM0)=(1,0). There is a 3-bit prescaler
(TMR3S2,TMR3S1,TMR3S0) which defines different
division ratio of TMR3 s clock source.
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Timer Counter 3
Bit No.
Label
Function
0~2
TMR3S2,
TMR3S1,
TMR3S0
To define the operating clock source (TMR3S2, TMR3S1, TMR3S0)
000: clock source/2
001: clock source/4
010: clock source/8
011: clock source/16
100: clock source/32
101: clock source/64
110: clock source/128
111: clock source/256
3
TE
To define the TMR3 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
To enable/disable timer counting (0=disabled; 1=enabled)
5
Unused bit, read as 0
6
7
TM0,
TM1
To define the operating mode (TM1, TM0)
01=Unused
10=Timer mode (internal clock)
11=Unused
00=Unused
TMR3C (25H) Register