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參數(shù)資料
| 型號(hào)： | HT82V36 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit CCD/CIS Analog Signal Processor |
| 中文描述： | 16位防治荒漠化公約/獨(dú)聯(lián)體模擬信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大小： | 123K |
| 代理商： | HT82V36 |
Timing Diagrams
HT82V36
Rev. 1.30
6
June 29, 2004
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain
(V/V)
Gain (dB)
Set to 0
Set to 0
Set to 0
MSB
LSB
1.0
1.013
.
.
.
5.43
5.85
0.0
0.12
.
.
.
14.7
15.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
.
.
.
1
1
0
0
1
1
0
0
1
1
0*
1
0
1
PGA Gain Register Settings
Note: * Power-on default value
Offset Register
Bits D8 through D0 control the offset range from 200mV to 200mV in 512 increments.
The coding for the offset registers is sign magnitude, with D8 as the sign bit. The Table shows the offset range as a
function of the bits D8 through D0.
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset
(mV)
MSB
LSB
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
.
.
.
1
0
0
.
.
.
1
0
0
1
0
0
1
0
0
1
0
0
1
0*
1
1
0
1
1
0
0.78
.
.
.
200
0
0.78
.
.
.
200
Note: * Power-on default value
$
!
&
'
(
$
#
"
6
7
8
6
%
Serial Write Operation Timing
$
!
&
'
(
$
#
"
)
7
8
6
%
Serial Read Operation Timing
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