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參數(shù)資料
| 型號(hào)： | HT82V36 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit CCD/CIS Analog Signal Processor |
| 中文描述： | 16位防治荒漠化公約/獨(dú)聯(lián)體模擬信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | HT82V36 |
Timing Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
t
ADCLK
Pixel Rate Clock
166
ns
t
ADH
ADCCLK Pulse High Width
80
ns
t
ADL
ADCCLK Pulse Low Width
80
ns
t
C1
CDSCLK1 Pulse Width
20
ns
t
C2
CDS Mode CDSCLK2 Pulse Width
20
ns
t
C3
SHA Mode CDSCLK2 Pulse Width
40
ns
t
C2ADF
CDSCLK2 Falling to ADCCLK Falling
60
ns
t
ADFC1
ADCCLK Falling to CDSCLK1 Rising
2
ns
t
ADFC2
ADCCLK Falling to CDSCLK2 Rising
2
ns
t
AD
Analog Sampling Delay
5
ns
Serial Interface
f
SCLK
Maximum SCLK Frequency
10
MHz
t
LS
SLOAD to SCLK Setup Time
10
ns
t
LH
SCLK to SLOAD Hold Time
10
ns
t
DS
SDATA to SCLK Rising Setup Time
10
ns
t
DH
SCLK Rising to SDATA Hold Time
10
ns
t
RDV
Falling to SDATA Valid
10
ns
Data Output
t
OD
Output Delay
8
ns
Latency (Pipeline Delay)
9
Cycles
HT82V36
Rev. 1.30
4
June 29, 2004
Functional Description
Integral Nonlinear (INL)
Integral nonlinear error refers to the deviation of each in-
dividual code from a line drawn from zero scale through
positive full scale. The point used as zero scale occurs 1
/2 LSB before the first code transition. Positive full scale
isdefinedasalevel1/2LSBbeyondthelastcodetransi-
tion. The deviation is measured from the middle of each
particular code to the true straight line.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed to 16-bit resolution indicates that all
4096 codes, respectively, must be present over all oper-
ating ranges.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage.
The offset error is the deviation of the actual first code
transition level from the ideal level.
Gain Error
The last code transition should occur for an analog
value 1/2 LSB below the nominal full-scale voltage.
Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal differ-
ence between the first and last code transitions.
Aperture Delay
The aperture delay is the time delay that occurs when a
samplingedgeisappliedtotheHT82V36untiltheactual
sample of the input signal is held. Both CDSCLK1 and
CDSCLK2 sample the input signal during the transition
from high to low, so the aperture delay is measured from
each clock s falling edge to the instant the actual inter-
nal sample is taken.
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