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參數(shù)資料
| 型號： | HT82V36 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit CCD/CIS Analog Signal Processor |
| 中文描述： | 16位防治荒漠化公約/獨聯(lián)體模擬信號處理器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 123K |
| 代理商： | HT82V36 |
HT82V36
Rev. 1.30
5
June 29, 2004
Internal Register Descriptions
Register
Name
Address
Data Bits
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
0
0
0
0
0
1
1
CDS onVoltage
Enable
Power
Down
Output
Delay
1byte
out
Reserved
0
0
1
Reserved
0
1
0
PGA
0
1
1
X
0
0
MSB
LSB
Reserved
1
0
0
Reserved
1
0
1
Offset
1
1
0
MSB
LSB
Reserved
1
1
1
Internal Register Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set to 0 Set to 0 Set to 1 Set to 1
CDS operation Clamp bias Power-down
Output delay
1 byte out
(High-byte only)
1=CDS mode*
1=2.5V*
1=On
1=On
1=On
0=SHA mode
0=2V
0=Off (Normal)* 0=Off*
0=Off*
Configuration Register Settings
Note: * Power-on default value
PGA Gain Register
Bits D7 and D6 in the register must be set low, and bits D5 through D0 control the gain range in 64 increments. See fig-
ure for a graph of the PGAgain versus PGAregister code. The coding for the PGAregister is straight binary, with an all
zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain
setting (5.85x).
ThePGAhasagainrangefrom1x(0dB)to5.85x(15.3dB),adjustablein64steps.TheFigureshowsthePGAgainasa
function of the PGAregister code. Although the gain curve is approximately linear in dB, the gain in V/V varies in non-
linear proportion with the register code, according to the following the equation: Gain=
5.85
1
4.85
(63
G
63
)
+
′
-
Where G is the decimal value of the gain register contents, and varies from 0 to 63.
PGA Gain Transfer Function
!
"
# $
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