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參數(shù)資料
| 型號： | HT82V24 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor |
| 中文描述： | 16位，15MSPS，3通道防治荒漠化公約/獨聯(lián)體模擬信號處理器 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 216K |
| 代理商： | HT82V24 |
HT82V24
Rev. 1.00
6
September 7, 2005
Configuration Register
The configuration register controls the HT82V24 s oper-
ating mode and bias levels. Bits D7 and D6 set the
clamp timing in WM mode and there are don't care in
ADI Mode. Bit D5 will configure the HT82V24 for the
3-channel (high) mode of operation. Setting the bit D4
high will enable the CDS mode of operation, and setting
this bit low will enable the SHA mode of operation.
Bit D3 sets the dc bias level of the HT82V24 s input
clamp. This bit should always be set high for the 4V
clamp bias, unless a CCD with a reset feed through
transient exceeding 2V is used. Setting the bit D3 low,
the clamp voltage is 3V. Bit D2 controls the power-down
mode. Setting bit D2 high will place the HT82V24 into a
very low power sleep mode. All register contents are
retained while the HT82V24 is in the power-down state.
Setting bit D1 high will select the 3V input range, other-
wise the 2V input range is selected.
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set to 0
Don t care
3 channels CDS operation Clamp bias
Power-down
Input
Range
1 byte out
(High-byte
only)
1=On*
1=CDS mode*
1=4V*
1=On
1=3V
1=On
0=Off
0=SHA mode
0=3V
0=Off
(Normal)*
0=2V*
0=Off*
Configuration Register Settings (ADI Mode)
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set to 1
Clamp Timing Control 3 channels CDS operation Clamp bias
Power-down
Input
Range
Output
Format
CDSREF1 CDSREF0
1=On*
1=CDS mode*
1=4V*
1=On
1=3V
1=Byte
output
0*
0*
0=Off
0=SHA mode
0=3V
0=Off
(Normal)*
0=2V*
0=Nibble
output*,**
Configuration Register Settings (Wolfson Mode)
Note: * Power-on default value
** It needs D5=0, D0=0 to enable Nibble output (1CH WM mode)
Bits D7 and D6 control the reset sample and clamp timing
Reset Sample and Clamp Timing (RS/CL)
Note: CDSREF=(CDSREF1,CDSREF0)
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