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參數(shù)資料
| 型號： | HT82V24 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor |
| 中文描述： | 16位，15MSPS，3通道防治荒漠化公約/獨聯(lián)體模擬信號處理器 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 216K |
| 代理商： | HT82V24 |
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
Temperature Range
t
A
Operating
0
70
C
Power Consumption
P
tot3
Total Power Consumption (3CH)
380
mW
P
tot2
Total Power Consumption (2CH)
340
mW
P
tot1
Total Power Consumption (1CH)
300
mW
Note: * means the full-scale input range select by configuration register
Timing Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
t
PRA
3-channel pixel rate
200
ns
t
PRB
2-channel (Even-Odd) pixel rate
133
ns
t
PRC
1-channel pixel rate
66
ns
t
ADCLK
ADCCLK Pulse Width
33
ns
t
C1
CDSCLK1 Pulse Width
15
30
ns
t
C2
CDSCLK2 Pulse Width
15
30
ns
t
C1C2
CDSCLK1 Falling to CDSCLK2 Rising
0
ns
t
ADC2
ADCCLK Rising to CDSCLK2 Falling
0
ns
t
C2ADR
CDSCLK2 Rising to ADCCLK Rising
5
ns
t
C2ADF
CDSCLK2 Falling to ADCCLK Falling
30
ns
t
C2C1
CDSCLK2 Falling to CDSCLK1 Rising
30
ns
t
AD
Analog Sampling Delay
5
ns
Serial Interface
f
SCLK
Maximum SCLK Frequency
10
MHz
t
LS
SLOAD to SCLK Setup Time
10
ns
t
LH
SCLK to SLOAD Hold Time
10
ns
t
DS
SDATA to SCLK Rising Setup Time
10
ns
t
DH
SCLK Rising to SDATA Hold Time
10
ns
t
RDV
Falling to SDATA Valid
10
ns
Data Output
t
OD
Output Delay
12
ns
HT82V24
Rev. 1.00
4
September 7, 2005
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