參數(shù)資料
型號: HT82M9BEE
廠商: Holtek Semiconductor Inc.
英文描述: USB Mouse Encoder 8-Bit MCU with EEPROM
中文描述: USB鼠標(biāo)編碼器8位微控制器帶有EEPROM
文件頁數(shù): 11/47頁
文件大小: 336K
代理商: HT82M9BEE
HT82M9BEE/HT82M9BAE
Rev. 1.20
11
August 13, 2007
The internal Timer/Event Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of the INTC0), caused by a Timer 1 overflow.
When the interrupt is enabled, the stack is not full and the
T1F is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
USB interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Once the interrupt request flags (T0F/T1F, USBF) are
set, they will remain in the INTC register until the inter-
rupts are serviced or cleared by a software instruction.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the CALL operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The HT82M9BEE/HT82M9BAE can operate in 6MHz or
12MHz system clocks. In order to make sure that the
USB SIE functions properly, user should correctly con-
figure the SCLKSELbit of the SCC Register. The default
system clock is 12MHz.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDToscillator still works within
a period of approximately 31 s. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determine by ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 31 s/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
8ms/5V. This time-out period may vary with tempera-
tures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
0 -
0 0
System Oscillator
-
0
< ) .
7 *
-
/
-
0
5 *
-
7 *
* -
/
-
*
/
1 2 /
!
0
/
Watchdog Timer
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