HT82M9AEE/HT82M9AAE
Rev. 1.20
27
August 13, 2007
Clock Control Register
SCC
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clockcontrolbit(USBCKEN),secondsuspendmodecontrolbit(SUSPEND2)andsystemclockselection(SCLKSEL).
Bit No.
Label
Read/Write
Option
Functions
0~2
PF0~PF2
R/W
Reserved, must set to 0 .
3
PF3
R/W
USBCKEN
USB clock control bit. When set to 1 , indicates a USBCK ON,
else USBCK OFF. The default value is 0 .
4
PF4
R/W
SUSPEND2
This bit is used to reduce power consumption in the suspend
mode. In the normal mode this bit must be cleared to zero(De-
fault= 0 ). In the HALT mode this bit should be set high to re-
duce power consumption and LVR with no function. In the USB
mode this bit cannot be set high.
5
PF5
R/W
Reserved, must set to 0 .
6
PF6
R/W
SCLKSEL
System clock 6MHz or 12MHz option, when working on exter-
nal oscillator mode. The default value is 0 .
0: Operating at external 12MHz mode
1: Operating at external 6MHz mode
The default value is 0 .
7
PF7
R/W
PS2_flag
This flag is used to show that the MCU is in PS2 mode (Bit=1).
ThisbitisR/WbyFWandwillbeclearedtozeroafterpower-on
reset. The default value is 0 .
SCC (0X1C) Register
Table High Byte Pointer for Current Table Read
TBHP
Bit No.
Label
Read/Write
Option
Functions
3~0
PGC3~PGC0
R/W
Store current table read bit11~bit8 data
TBHP (0X1F) Register
Options
No.
Option
1
WDT clock source: RC (system/4) (default: T1)
2
WDT clock source: enable/disable for normal mode (default: disable)
3
PA0~PA7, PB4/SDA, PB7/SCL wake-up by bit (PA2, PA3 both wake-up by falling or rising edge)
(default: non wake-up)
4
PA0~PA7 pull-high by bit (default: pull-high)
5
PB pull-high by bit (default: pull-high)
6
LVR enable/disable (default: enable)
7
PA0~PA3, PB2, PB3 pull-low by bit (default: non pull-low 30k )
8
CLR WDT , 1 or 2 instructions
9
TBHP enable/disable (default: disable)
10
PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS)