參數(shù)資料
型號: HT82M9AEE
廠商: Holtek Semiconductor Inc.
英文描述: USB Mouse Encoder 8-Bit MCU with EEPROM
中文描述: USB鼠標編碼器8位微控制器帶有EEPROM
文件頁數(shù): 10/48頁
文件大?。?/td> 330K
代理商: HT82M9AEE
HT82M9AEE/HT82M9AAE
Rev. 1.20
10
August 13, 2007
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
tosettheenable/disableandtheinterruptrequestflags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
Access of the corresponding USB FIFO from PC
The USB suspend signal from PC
The USB resume signal from PC
USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO of the
HT82M9AEE/ HT82M9AAE, the corresponding request
bit of the USR is set, and a USB interrupt is triggered. So
user can easily decide which FIFO is accessed. When
the interrupt has been served, the corresponding bit
should be cleared by firmware. When the
HT82M9AEE/HT82M9AAE receives a USB Suspend
signal from the Host PC, the suspend line (bit0 of the
USC) of the HT82M9AEE/HT82M9AAE is set and a
USB interrupt is also triggered.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0= disable)
2, 5, 7
Unused bit, read as 0
3
ETI
Controls the Timer/Event Counter interrupt (1=enable; 0=disable)
4
USBF
USB interrupt request flag (1=active; 0=inactive)
6
TF
Internal timer/event counter request flag (1:active; 0:inactive)
INTC (0BH) Register
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
takeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by
executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6~7
Unused bit, read as 0
Status (0AH) Register
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