參數(shù)資料
型號(hào): HT82K68A
廠(chǎng)商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片,用于多I/O口及多媒體器件)
中文描述: 8位高性能外圍接口芯片為多個(gè)I / O產(chǎn)品和多媒體應(yīng)用(8位高性能外圍接口集成芯片,用于多的I / O口及多媒體器件)
文件頁(yè)數(shù): 8/40頁(yè)
文件大小: 255K
代理商: HT82K68A
Mode
Program Counter
11
10
9
8
7
6
5
4
3
2
1
0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
Timer counter overflow
0
0
0
0
0
0
0
0
1
0
0
0
Skip
PC+2
Loading PCL
11
10
9
8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
HT82K68A
8
December 8, 2000
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Location 008H
This area is reserved for the timer counter in-
terruptserviceprogram.Iftimerinterruptre-
sults from a timer counter overflow, and if the
interrupt is enabled and the stack is not full,
the program begins execution at location
008H.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m]
(the current page, 1 page=256 words) and
TABRDL [m] (the last page) transfer the con-
tents of the lower-order byte to the specified
data memory, and the higher-order byte to
TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined,
the other bits of the table word are trans-
ferred to the lower portion of TBLH, the re-
maining 1 bit is read as 0. The Table
Higher-order byte register (TBLH) is read
only. The TBLH is read only and cannot be re-
stored. If the main routine and the ISR (Inter-
rupt Service Routine) both employ the table
read instruction, the contents of the TBLH in
the main routine are likely to be changed by
the table read instruction used in the ISR. Er-
rors can occur. In other words, using the table
read instruction in the main routine and the
ISR simultaneously should be avoided. How-
ever, if the table read instruction has to be ap-
plied in both the main routine and the ISR,
the interrupt is supposed to be disabled prior
to the table read instruction. It will not be en-
abled until the TBLH has been backed up.
The table pointer (TBLP) is a read/write regis-
ter (07H), which indicates the table location.
Before accessing the table, the location must be
placed in TBLP. All table related instructions
need 2 cycles to complete the operation. These
areasmayfunctionasnormalprogrammemory
depending upon the requirements.
=
/ =
>&
.
+ > &
& 0
4 & 0
# < : & . & 5 3 4 & @ 6
=
# < : & . & 5 3 4 & @ 6
1 8 8 =
A & & % & & 1 & &
8 8 =
Program memory
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