參數(shù)資料
型號(hào): HT82K68A
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片,用于多I/O口及多媒體器件)
中文描述: 8位高性能外圍接口芯片為多個(gè)I / O產(chǎn)品和多媒體應(yīng)用(8位高性能外圍接口集成芯片,用于多的I / O口及多媒體器件)
文件頁數(shù): 18/40頁
文件大?。?/td> 255K
代理商: HT82K68A
HT82K68A
18
December 8, 2000
Each I/O line has its own control register (PAC,
PBC, PCC, PDC, PEC) to control the input/out-
put configuration. With this control register,
CMOS output or schmitt trigger input with or
without pull-high resistor (mask option) struc-
tures can be reconfigured dynamically (i.e.,
on-the-fly) under software control. To function as
an input, the corresponding latch of the control
register must write 1 . The pull-high resistance
will exhibit automatically if the pull-high option
is selected. The input source(s) also depend(s) on
the control register. If the control register bit is
1 , input will read the pad state. If the control
register bit is 0 , the contents of the latches will
move to the internal bus. The latter is possible in
read-modify-write instruction. For output func-
tion, CMOS is the only configuration. These con-
trol registers are mapped to locations 13H, 15H,
17H, 19H and 1BH.
After a chip reset, these input/output lines stay
at high levels or floating (mask option). Each
bit of these input/output latches can be set or
cleared by the SET [m].i or CLR [m].i (m=12H,
14H, 16H, 18H or 1AH) instruction.
Some instructions first input data and then fol-
low the output operations. For example, the
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]
instructions read the entire port states into the
CPU, execute the defined operations
(bit-operation), and then write the results back
to the latches or the accumulator.
Each line of port Aand port C [0:3] has the capa-
bility to wake-up the device.
C
*
C
C
*
C
& 1
-& &
$ &
& &
-
& +
&
" & -
5 ! & D & ' 2 & . " 6
< :
-
<
. . :
! ' ! (
1 ' 1 (
' (
' (
' ,
< &
< &
Input/output ports
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