Instruction(s)
Table Location
11
10
9
8
7
6
5
4
3
2
1
0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
0
1
1
@7
@6
@5
@4
@3
@2
@1
@0
HT82K68E
9
August 8, 2000
Preliminary
Note: *11~*0: Table location bits
@7~@0: Table location bits
P11~P8: Current program counter bits
Stack register
STACK
This is a special part of the memory which is
used to save the contents of the program coun-
ter(PC)only.Thestackisorganizedintosixlev-
els and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledgement, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be re-
corded but the acknowledgement will be inhib-
ited. When the stack pointer is decremented (by
RETorRETI),theinterruptwillbeserviced.This
feature prevents stack overflow allowing the pro-
grammer to use the structure more easily. In a
similar case, if the stack is full and a CALL
subsequentlyexecuted,stackoverflowoccursand
the first entry will be lost (only the most recent
four return addresses are stored).
is
Data memory
RAM
The data memory is designed with 184
It is divided into two functional groups: special
function registers and general purpose data
memory (160 8). Most of them are read/write,
but some are read only.
8 bits.
The special function registers include the Indi-
rect Addressing register 0 (00H), the Memory
Pointer register 0 (MP0;01H), the Indirect Ad-
dressing register 1 (02H), the Memory Pointer
register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte
register (PCL;06H), the Table Pointer
(TBLP;07H), the Table Higher-order byte regis-
ter (TBLH;08H), the Watchdog Timer option Set-
ting register (WDTS;09H), the Status register
& !
& !
!
#
1 #
1 # =
-
!
!
!
1
1
. &
! ! & )
5 4 & 1 "6
. &
! ! & )
=
=
=
2 =
, =
3 =
4 =
( =
/ =
7 =
! =
1 =
=
=
=
8 =
=
=
=
2 =
, =
3 =
4 =
( =
/ =
7 =
! =
1 =
=
=
=
8 =
8 8 =
A & B
& &
=
4 =
RAM mapping