參數(shù)資料
型號: HT82K68
廠商: Holtek Semiconductor Inc.
英文描述: Multimedia Keyboard Encoder OTP
中文描述: 多媒體鍵盤編碼器檢察官辦公室
文件頁數(shù): 14/40頁
文件大?。?/td> 260K
代理商: HT82K68
HT82K68E
14
August 8, 2000
Preliminary
cuted to clear the WDT; otherwise, the WDT may
reset the chip because of the time-out.
Power down operation
HALT
The HALT mode is initialized by the HALT in-
struction and results in the following...
The system oscillator will turn off but the
WDT oscillator keeps running (if the WDT os-
cillator is selected).
The contents of the on chip RAM and regis-
ters remain unchanged.
WDT and WDT prescaler will be cleared and
recount again (if the WDT clock has come
from the WDT oscillator).
All I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means
of an external reset, an external falling edge
signal on port A and port C [0:3] or a WDT over-
flow. An external reset causes a device initializa-
tion and the WDT overflow performs a warm
reset . Examining the TO and PD flags, the rea-
son for chip reset can be determined. The PD flag
isclearedwhensystempower-uporexecutingthe
CLR WDT instruction and is set when the HALT
instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that
only resets the PC and SP, the others keep their
original status.
The port A or port C [0:3] wake-up can be con-
sidered as a continuation of normal execution.
Each bit in port A can be independently se-
lected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro-
gram will resume execution of the next instruc-
tion.
Once a wake-up event occurs, and the system
clock comes from a crystal, it takes 1024 t
SYS
(system clock period) to resume normal opera-
tion. In other words, the HT82K68E will insert
a dummy period after the wake-up. If the sys-
tem clock comes from an RC oscillator, it contin-
ues operating immediately. If the wake-up
results in next instruction execution, this will
execute immediately after the dummy period is
completed.
To minimize power consumption, all I/O pins
should be carefully managed before entering
the HALT status.
Reset
Therearethreewaysinwhicharesetcanoccur:
RESET reset during normal operation
RESET reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a warm reset that just resets the PC
and SP, leaving the other circuits to remain in
their original state. Some registers remain un-
changed during other reset conditions. Most
registers are reset to the
initial condition
" & . < + ,
/ : 0
-
& .
( : 0
/ :: &
-
& :
- ' -
.
-
Watchdog Timer
&:
$ & &
Reset timing chart
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