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參數(shù)資料
| 型號： | HT82J97E-28SOP-A |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | USB Joystick Encoder 8-Bit OTP MCU |
| 中文描述： | USB搖桿編碼器8位微控制器檢察官辦公室 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 314K |
| 代理商： | HT82J97E-28SOP-A |
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HT82J97E
Rev. 1.30
24
May 10, 2004
Clock Control Register SCC (Address 0X1C)
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clockcontrolbit(USBCKEN),secondsuspendmodecontrolbit(SUSPEND2)andsystemclockselection(SCLKSEL).
Register
Bits
Labels
Read/Write
Option
Functions
SCC
(0X1C)
2~0
PF2~PF0
R/W
Reserved
3
PF3
R/W
USBCKEN
USB clock control bit. When set to
USBCK ON, else USBCK OFF. Default value is 0 .
1 , indicates a
4
PF4
R/W
SUSPEND2
When set to 1 , enables a 7.5k
D-pin to 5V VDD. Default value is 0 .
resistor connected to
5
PF5
R/W
Reserved
6
PF6
R/W
SCLKSEL
System clock 6MHz or 12MHz option, when working on
external oscillator mode. Default value is 0 .
0: Operating at external 12MHz mode
1: Operating at external 6MHz mode
Default value is 0 .
7
PF7
R/W
PS2_flag
This flag is used to show that the MCU is in PS2 mode
(Bit=1). This bit is R/W by FW and will be cleared to zero
after power-on reset. The default is 0 .
ADC Status and Control Register ADC (Address 0X1D)
The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference
voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal
power supplies of the MCU (VDD and VSS). The VRLand VRH are used to set the minimal and maximal boundaries of
the full-scale range of the A/D converter. If an analog input, VRL or VRH is not used for A/D conversion, it can also be
used as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the
configurations and A/D clock sources of the A/D converter and controls the operation of the A/D converter.
Register Bits
Labels
Read/Write
Option
Functions
ADC
(0X1D)
2~0
PFC2~PFC0
R/W
SEL_CH
These four bits selects one of the eight ADC channels
for conversion. Channels 0 to 5 correspond to inputs
AD0~AD5 on port pins PB0-PB5 respectively. Chan-
nels 6 and 7 are the ADC reference inputs VRH and
VRL, on port pins PB6 and PB7 respectively.
000: AD0 (PB0); 001: AD1 (PB1)
010: AD2 (PB2); 011: AD3 (PB3)
100: AD4 (PB4); 101: AD5 (PB5)
110: AD6 or VRL (PB6); 111: AD7 or VRH (PB7)
Default value is 000 B.
4~3
PFC4~PFC3
R/W
SEL_CLK
Selecting ADC operating clock.
00: 6MHz (Default clock)
01: 3MHz
10: 1.5MHz
11: 0.75MHz
5
PFC5
R/W
START
Start of ADC conversion. High active. Default value is
0
6
PFC6
R/W
ADON
Enable pin. ADON=1, Enable ADC block.
Default value is 0 .
7
PFC7
R/W
EOCB
End of conversion. This read-only status bit is cleared
when a conversion is completed, indicating that the
ADC Data Register contains a valid result.
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相關(guān)代理商/技術(shù)參數(shù) |
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