參數(shù)資料
型號: HT82J97E-28SOP-A
廠商: Holtek Semiconductor Inc.
英文描述: USB Joystick Encoder 8-Bit OTP MCU
中文描述: USB搖桿編碼器8位微控制器檢察官辦公室
文件頁數(shù): 11/46頁
文件大小: 314K
代理商: HT82J97E-28SOP-A
HT82J97E
Rev. 1.30
11
May 10, 2004
wake-up event occurs, it takes 1024 t
SYS
(system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearefour waysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
USB reset
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PDF and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset, WDT
begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
Reset Circuit
+
(
!
+
2
#
, "
!
!
(
!
6
(
,
Reset Configuration
(
6
$
( (
!
Reset Timing Chart
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