參數(shù)資料
型號(hào)： HT82J97E-20SOP-A
廠商： Holtek Semiconductor Inc.
英文描述： USB Joystick Encoder 8-Bit OTP MCU
中文描述： USB搖桿編碼器8位微控制器檢察官辦公室
文件頁(yè)數(shù)： 6/46頁(yè)
文件大?。?/td> 314K
代理商： HT82J97E-20SOP-A
HT82J97E
Rev. 1.30
6
May 10, 2004
Stack Register
STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
Data Memory
RAM for Bank 0
The data memory is designed with 96 8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(96 8). Most are read/write, but some are read only.
The special function registers include the indirect ad-
dressing registers (R0;00H, R1;02H), Bank register (BP,
04H), PWM1 duty register (0DH), PWM2 duty regis-
ter(0EH), Timer/Event Counter higher order byte regis-
ter (TMRH;0FH), Timer/Event Counter lower order byte
register (TMRL;10H), Timer/Event Counter control reg-
ister (TMRC;11H), program counter lower-order byte
register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointers (TBLP;07H, TBHP;1FH), table higher-order
byte
register
(TBLH;08H),
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H), PWM Base
Period Register (18H), I/O control registers (PAC;13H,
PBC;15H, PCC;17H). USB/PS2 status and control reg-
ister (USC;1AH), USB endpoint interrupt status register
(USR;1BH), system clock control register (SCC;1CH).
A/D converter status and control register (ADSC;1DH)
and A/D converter result register (ADR;1EH). The re-
maining space before the 20H is reserved for future ex-
status
register
panded usage and reading these locations will get
00H . The general purpose data memory, addressed
from 20H to 7FH, is used for data and control informa-
tion under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
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Bank 0 RAM Mapping
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