參數(shù)資料
型號： HT82J97E-20SOP-A
廠商： Holtek Semiconductor Inc.
英文描述： USB Joystick Encoder 8-Bit OTP MCU
中文描述： USB搖桿編碼器8位微控制器檢察官辦公室
文件頁數(shù)： 18/46頁
文件大小： 314K
代理商： HT82J97E-20SOP-A
HT82J97E
Rev. 1.30
18
May 10, 2004
Function
Name
Read/Write
Description
Request
R/W
After setting the other desired status, FIFO can be requested by setting this bit high active.
After work has been done, this bit must be set low.
Tx
R/W
RepresentsthedirectionandtransitionendoftheMCUaccesses.Whenbeingsetaslogic
1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to
logic 0 before terminating the request to represent a transition end. For reading action, this
bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1
after work is done.
Clear
R/W
Represents MCUclear requested FIFO, even if FIFO is not ready.
Sel_pipe1
Sel_pipe0
R/W
Determines which FIFO is desired, 00 for FIFO 0, 01 for FIFO 1
Set CMD
R/W
Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So,
even if the MCU is busy, nothing is missed by the SETUP command from the host.
Ready
R
Indicates that the desired FIFO is ready to work.
Len0
R/W
Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after
the next valid SETUP token is received.
Misc Function Table
The HT82J97E has two 8 8 bidirectional FIFO for the
two endpoints (control and Interrupt). User can easily
read/write the FIFO data by accessing the correspond-
ing FIFO pointer register (FIFO0, FIFO1). The following
aretwoexamplesforreadingandwritingtheFIFOdata:
HT82J97E FIFO is read by packet. To read from FIFO,
the following should be followed:
Select one set of FIFO, set in the read mode (MISC
TX bit = 0), and set the REQ bit to 1 .
Check the ready bit until the status = 1
Read through the FIFO pointer register, and record
the data number that has been read.
Repeat steps 2 and 3 until the ready bit becomes 0
which indicates the end of the FIFO data reading.
Set MISC TX bit = 1
Clear the REQ bit to 0. Complete reading.
User reads the data through the FIFO pointer register,
user has to record the number of bytes to be read. The
HT82J97E allows a maximum of 8 bytes of data in each
packet.
The HT82J97E FIFO is written by packet. To write to
FIFO, the following should be followed:
Select a set of FIFO, set in the write mode (MISC TX
bit = 1), and set the REQ bit to 1
Check the ready bit until the status = 1
Write through the FIFO pointer register and take down
the data number that has been written
Repeat steps 2 and 3 until writing is complete or the
ready bit becomes 0 which indicates that the FIFO no
longer allows any data writing.
Set MISC TX bit = 0
Clear the REQ bit to 0. Complete writing.
User writes the data through the FIFO pointer register,
user has to record the number of bytes that have been
written. The HT82J97E allows a maximum of 8 bytes of
data in each packet.
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