HT48R50A-1
Rev. 1.10
20
July 2, 2001
0. The internal clock source can be selected as
coming from (can always be optioned) or f
RTC
(enabled only system oscillator in the Int.
RC+RTC mode) by ROM code option. The exter-
nalclockinputallowstheusertocountexternal
events, measure time intervals or pulse widths,
or to generate an accurate time base and PFD
signals.
Using the internal clock sources, there are 2
reference time-bases for Timer/Event Counter
1. The internal clock source can be selected as
coming from f
SYS
/4 (can always be optioned) or
f
RTC
(enable only the system oscillator in the
Int. RC+RTC mode) by ROM code option. The
external clock input allows the user to count ex-
ternal events, measure time intervals or pulse
widths or to generate an accurate time base.
There are 2 registers related to the Timer/Event
Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two
physical registers are mapped to TMR0 location;
writingTMR0makesthestartingvaluebeplaced
intheTimer/EventCounter0preloadregisterand
reading TMR0 gets the contents of the
Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which de-
finessomeoptions.
There are 3 registers related to Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H),
TMR1C (11H). Writing TMR1L will only put
the written data to an internal lower-order byte
buffer (8 bits) and writing TMR1H will transfer
the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L
preload
registers,
Timer/Event Counter 1 preload register is
changed by each writing TMR1H operations.
Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destina-
tion and the lower-order byte buffer, respec-
tively. Reading the TMR1L will read the
contents of the lower-order byte buffer. The
TMR1C is the Timer/Event Counter 1 control
respectively.
The
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Timer/Event Counter 1