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參數(shù)資料
| 型號(hào)： | HT48R50A |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 10/46頁 |
| 文件大?。?/td> | 1037K |
| 代理商： | HT48R50A |
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HT48R50A-1
Rev. 1.10
10
July 2, 2001
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
destination of the lower-order byte in the ta-
ble is well-defined, the other bits of the table
word are transferred to the lower portion of
TBLH, and the remaining 1-bit words are
read as "0". The Table Higher-order byte reg-
ister (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which
indicates the table location. Before accessing
the table, the location must be placed in the
TBLP. The TBLH is read only and cannot be
restored. If the main routine and the ISR (In-
terrupt Service Routine) both employ the ta-
ble read instruction, the contents of the
TBLH in the main routine are likely to be
changed by the table read instruction used in
the ISR. Errors can occur. In other words, us-
ing the table read instruction in the main rou-
tine and the ISR simultaneously should be
avoided. However, if the table read instruc-
tionhastobeappliedinboththemainroutine
and the ISR, the interrupt is supposed to be
disabled prior to the table read instruction. It
will not be enabled until the TBLH has been
backed up. All table related instructions re-
quire two cycles to complete the operation.
These areas may function as normal program
memory depending upon the requirements.
Stack register
STACK
This is a special part of the memory which is
used to save the contents of the program coun-
ter (PC) only. The stack is organized into 6 lev-
els and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledge signal, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledge signal will be in-
hibited. When the stack pointer is decremented
(by RET or RETI), the interrupt will be ser-
viced. This feature prevents stack overflow al-
lowing the programmer to use the structure
more easily. In a similar case, if the stack is full
and a "CALL" is subsequently executed, stack
overflow occurs and the first entry will be lost
(only the most recent 6 return addresses are
stored).
Data memory
RAM
The data memory is designed with 186 8 bits.
The data memory is divided into two func-
tional groups: special function registers and
general purpose data memory (160 8). Most
are read/write, but some are read only.
The special function registers include the indi-
rect addressing registers (R0;00H, R1;02H),
Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register
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相關(guān)代理商/技術(shù)參數(shù) |
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| HT48R50A-1 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
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