
HT48R10A-1
Rev. 1.20
18
July 2, 2001
on pull-high options). Each bit of these in-
put/outputlatchescanbesetorclearedby"SET
[m].i" and "CLR [m].i" (m=12H, 14H or 16H) in-
structions.
Some instructions first input data and then fol-
low the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA [m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accu-
mulator.
Each line of port A has the capability of wak-
ing-up the device. The highest 3-bit of port C are
not physically implemented; on reading them a
"0" is returned whereas writing then results in a
no-operation. See Application note.
There is a pull-high option available for all I/O
ports (byte option). Once the pull-high option of
an I/O port is selected, all I/O lines have
pull-high resistors. Otherwise, the pull-high re-
sistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode
will cause a floating state.
The PB0 and PB1 are pin-shared with BZ and
BZ signal, respectively. If the BZ/BZ option is
selected, the output signal in output mode of
PB0/PB1 will be the PFD signal generated by
timer/event counter overflow signal. The input
mode always remaining its original functions.
Once the BZ/BZ option is selected, the buzzer
output signals are controlled by PB0 data regis-
ter only. The I/O functions of PB0/PB1 are
shown below.
PB0 I/O
I
I O O O O O O O O
PB1 I/O
I O I
I I O O O O O
PB0 Mode
x x C B B C B B B B
PB1 Mode
x C x x x C C C B B
PB0 Data
x x D 0 1 D
0
0 1 0 1
PB1 Data
x D x x x D
1
D D x x
PB0 Pad Status I
I D 0 B D
0
0 B 0 B
PB1 Pad Status I D I
I I D
1
D D 0 B
Note:
I input,
B buzzer option, BZ or BZ,
care
C CMOS output
O output,
D, D
0
, D
1
data,
x don't
7
D
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7 D ( 2 8
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E
E
!
E
* . / # * (1 /
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"
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F
) * #
* . ( 2 D
F
) * #
* . ( 2 D & * . / # * ( F
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Input/output ports