HT48R70A-1/HT48C70-1
Rev. 1.60
16
June 9, 2004
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are imple-
mented in the microcontroller. The Timer/Event Counter
0 contains an 16-bit programmable count-up counter
and the clock may come from an external source or from
the system clock divided by 4 or RTC.
The Timer/Event Counter 1 contains an 16-bit program-
mable count-up counter and the clock may come from
an external source or from the system clock divided by 4
or RTC.
Using the internal clock sources, there are 2 reference
time-bases for Timer/Event Counter 0. The internal
clock source can be selected as coming from f
TID
(can
always be optioned) or f
RTC
(enabled only system oscil-
lator in the Int. RC+RTC mode) by options.
Using the internal clock sources, there are 2 reference
time-bases for Timer/Event Counter 1. The internal
clock source can be selected as coming from f
SYS
/4
(can always be optioned) or f
RTC
(enable only the sys-
tem oscillator in the Int. RC+RTC mode) by options.
Usingexternalclockinputallowstheusertocountexter-
nal events, measure time internals or pulse widths, or
generate an accurate time base. While using the inter-
nal clock allows the user to generate an accurate time
base.
There are 3 registers related to the Timer/Event Counter
0;TMR0H ([0CH]), TMR0L ([0DH]), TMR0C ([0EH]). Writ-
ing TMR0L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR0H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR0H and TMR0L preload
registers,respectively.TheTimer/EventCounter1preload
register is changed by each writing TMR0H operations.
Reading TMR0H will latch the contents of TMR0H and
TMR0L counters to the destination and the lower-order
byte buffer, respectively. Reading the TMR0Lwill read the
contents of the lower-order byte buffer. The TMR0C is the
Timer/Event Counter 1 control register, which defines the
operating mode, counting enable or disable and active
edge.
There are 3 registers related to Timer/Event Counter 1;
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H op-
erations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
Label (TMR0C)
Bits
Function
0~2
Unused bit, read as 0
T0E
3
To define the TMR0 active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
T0ON
4
To enable or disable timer 0 counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
T0M0
T0M1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C Register
Label (TMR1C)
Bits
Function
0~2
Unused bit, read as 0
T1E
3
To define the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
T1ON
4
To enable or disable timer 1 counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
T1M0
T1M1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C Register