參數(shù)資料
型號(hào)： HT48C70
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit Microcontroller Series
中文描述： 8位微控制器系列
文件頁(yè)數(shù)： 14/40頁(yè)
文件大?。?/td> 273K
代理商： HT48C70
HT48R70A-1/HT48C70-1
Rev. 1.60
14
June 9, 2004
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
thePCandSP;theothersremainintheiroriginalstatus.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
1 before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
SYS
(system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The RTC oscillator still runs in the HALT mode (if the
RTC oscillator is enabled).
Reset
There are three ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PDF and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
SP
Points to the top of the stack
=
=
D
1 E
D
1 E
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
'
(
!
'
.
#
) "
!
!
(
!
; >
(
)
Reset Configuration
(
;
$
( (
!
Reset Timing Chart
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