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參數(shù)資料
| 型號： | HT48C70 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit Microcontroller Series |
| 中文描述： | 8位微控制器系列 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 273K |
| 代理商： | HT48C70 |
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HT48R70A-1/HT48C70-1
Rev. 1.60
13
June 9, 2004
frequency reference, but two external capacitors in
OSC1 and OSC2 are required. If the internal RC oscilla-
tor is used, the OSC1 and OSC2 can be selected as
32768Hz crystal oscillator (RTC OSC). Also, the fre-
quencies of the internal RC oscillator can be 3.2MHz,
1.6MHz,800kHzand400kHz(dependsontheoptions).
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDToscillator still works within
aperiodofapproximately65 s@5V.TheWDToscillator
can be disabled by options to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), RTC clock or instruction
clock (system clock divided by 4), determines the op-
tions. This timer is designed to prevent a software mal-
function or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by options. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation. The RTC clock is enabled only in the in-
ternal RC+RTC mode.
Once the internal WDT oscillator (RC oscillator with a
period of 65 s@5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 17ms@5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.1s@5V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for users defined flags, which can be used to
indicate some specified status.
If the device operates in a noisy environment, using the
on-chipRCoscillator(WDTOSC)or32kHzcrystaloscil-
lator (RTC OSC) is strongly recommended, since the
HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS Register
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO . But in the HALT
mode, the overflow will initialize a warm reset and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted;externalreset(alowleveltoRES),softwarein-
structionanda HALT instruction.Thesoftwareinstruc-
tion include
CLR WDT and the other set
CLR
WDT1 and CLR WDT2 . Of these two types of instruc-
tion, only one can be active depending on the option
CLR WDT times selection option . If the CLR WDT is
selected (i.e. CLRWDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In the
case that CLR WDT1 and CLR WDT2 are chosen
(i.e. CLRWDT times equal two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
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Watchdog Timer
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