- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385399 > HT48C05 (Holtek Semiconductor Inc.) Cost-Effective I/O Type 8-Bit MCU PDF資料下載
參數(shù)資料
| 型號： | HT48C05 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Cost-Effective I/O Type 8-Bit MCU |
| 中文描述： | 成本效益的I / O型8位微控制器 |
| 文件頁數(shù)： | 9/38頁 |
| 文件大?。?/td> | 264K |
| 代理商： | HT48C05 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
9
June 9, 2004
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stackisnotfullandtheexternalinterruptisactive,asub-
routine call to location 04H will occur. The interrupt re-
quest flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the
instruction is executed or the EMI bit and the related in-
terrupt control bit are set to 1 (of course, if the stack is
RETI
not full). To return from the interrupt subroutine, RET
or RETI may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
External Interrupt
1
04H
b
Timer/EventCounterOverflow
2
08H
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), enable timer/event
counter bit (ETI), enable external interrupt bit (EEI) and
enable master interrupt bit (EMI) constitute an interrupt
control register (INTC) which is located at 0BH in the
data memory. EMI, EEI, ETI are used to control the en-
abling/disabling of interrupts. These bits prevent the re-
quested interrupt from being serviced. Once the
interrupt request flags (TF, EIF) are set, they will remain
in the INTC register until the interrupts are serviced or
cleared by a software instruction.
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Controls the external interrupt (1= enabled; 0= disabled)
2
ETI
Controls the timer/event counter interrupt (1= enabled; 0= disabled)
3
Unused bit, read as 0
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
TF
Internal timer/event counter request flag (1= active; 0= inactive)
6
Unused bit, read as 0
7
Unused bit, read as 0
INTC Register
Labels
Bits
Function
C
0
Cissetiftheoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottake
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by exe-
cuting the HALT instruction.
TO
5
TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
6
Unused bit, read as 0
7
Unused bit, read as 0
Status Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT48C06 | Cost-Effective I/O Type 8-Bit MCU |
| HT48C10-1 | 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器，用于多I/O接口設(shè)備) |
| HT48C50-1 | 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器，用于多I/O接口設(shè)備) |
| HT48C50- | 8-BIT MICROCONTROLLER |
| HT48C70-1 | I/O Type 8-Bit MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT48C05_08 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective I/O Type 8-Bit MCU |
| HT48C06 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective I/O Type 8-Bit MCU |
| HT48C062 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:八位高性能精簡指令集單片機，專為經(jīng)濟型多輸入輸出控制的產(chǎn)品設(shè)計 |
| HT48C062_08 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective I/O Type 8-Bit MCU |
| HT48C10 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:8-Bit Microcontroller Series |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。