參數(shù)資料
型號(hào): HT48C05
廠商: Holtek Semiconductor Inc.
英文描述: Cost-Effective I/O Type 8-Bit MCU
中文描述: 成本效益的I / O型8位微控制器
文件頁(yè)數(shù): 15/38頁(yè)
文件大?。?/td> 264K
代理商: HT48C05
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
15
June 9, 2004
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 6-bit of port C and 5 bits of port B
are not physically implemented; on reading them a 0 is
returned whereas writing then results in a no-operation.
See Application note.
There is a pull-high option available for all I/O lines.
Once the pull-high option is selected, all I/O lines have
pull-high resistors. Otherwise, the pull-high resistors are
absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PB0/PB1 will be the PFD signal
generated by timer/event counter overflow signal. The
input mode always remaining its original functions.
Once the BZ/BZ option is selected, the buzzer output
signals are controlled by PB0 data register only. The I/O
functions of PB0/PB1 are shown below.
PB0 I/O
I
I
I
I
O
O O O
O
O
PB1 I/O
I
O
O
O
I
I
I
O
O
O
PB0/PB1 Mode
x
C
B
B
C
B B C
B
B
PB0 Data
x
x
0
1
D
0 1 D
0
0
1
PB1 Data
x
D
x
x
x
x
x D
1
x
x
PB0 Pad Status
I
I
I
I
D
0 B D
0
0
B
PB1 Pad Status
I
D
0
B
I
I
I D
1
0
B
Note:
I: input; O: output; D, D
0
, D
1
: data;
B: buzzer option, BZ or BZ; x: don't care
C: CMOS output
The PC0 and PC1 are pin-shared with INT, TMR and
pins respectively.
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
Low Voltage Reset
LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~V
LVR
, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The LVR includes the following specifications:
The low voltage (0.9V~V
LVR
) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
The LVR uses the OR function with the external
RES signal to perform chip reset.
TherelationshipbetweenV
DD
andV
LVR
isshownbelow.
Note:
V
OPR
is the voltage range for proper chip opera-
tion at 4MHz system clock.
1 C 1
3 C
C
C 5
-
1 C 1
1 C 1
-
C 5
% + % $
' # 0
% + % $
D
D
! 0
& % $ ' #
% + % $
-
% $ % ( $
0 $
%
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms
delay enters the reset mode.
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