HT46R62/HT46C62
Rev. 1.60
19
July 14, 2005
on PD0/PD1/PD2 (if PD0/PD1/PD2 is operating in out-
put mode). The I/O functions of PD0/PD1/PD2 are as
shown.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0
PD1
PD2
Logical
Input
Logical
Output
Logical
Input
PWM0
PWM1
PWM2
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
Timer
Preload
Value
PA3 Data
Register
PA3 Pad
State
PFD
Frequency
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
f
TMR
/[2 (M-N)]
Note:
X stands for unused
U stands for unknown
M is 256 for PFD
N is preload value for timer/event counter
f
TMR
is input clock frequency for timer/event
counter
PWM
The microcontroller provides 3 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1/PD2. The PWM channels have their data reg-
isters denoted as PWM0 (1AH), PWM1 (1BH) and
PWM2 (1CH). The frequency source of the PWM coun-
ter comes from f
SYS
. The PWM registers are three 8-bit
registers. The waveforms of PWM outputs are as
shown. Once the PD0/PD1/PD2 are selected as the
PWM outputs and the output function of PD0/PD1/PD2
are enabled (PDC.0/PDC.1/ PDC.2= 0 ), writing 1 to
PD0/PD1/PD2 data register will enable the PWM output
function and writing 0 will force the PD0/PD1/PD2 to
stay at 0 .
A(6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
Modulation cycle i
(i=0~3)
i<AC
DC+1
64
i AC
DC
64
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Input/Output Ports