參數(shù)資料
型號(hào)： HT46R62
廠(chǎng)商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 15/46頁(yè)
文件大小： 401K
代理商： HT46R62
HT46R62/HT46C62
Rev. 1.60
15
July 14, 2005
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT,RTC,TimeBase
Cleared. After master reset,
WDT starts counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Pointstothetopofthestack
Timer/Event Counter
One timer/event counters (TMR) are implemented in the
microcontroller. The Timer/Event Counter contains a
8-bit programmable count-up counter and the clock may
come from an external source or an internal clock
source. An internal clock source comes from f
SYS
. The
external clock input allows the user to count external
events, measure time intervals or pulse widths, or to
generate an accurate time base.
There are two registers related to the Timer/Event
Counter; TMR ([0DH]) and TMRC ([0EH]). Two physical
registers are mapped to TMR location; writing TMR puts
the starting value in the Timer/Event Counter register
and reading TMR takes the contents of the Timer/Event
Counter.TheTMRCisatimer/eventcountercontrolreg-
ister, which defines some options counting enable or
disable and an active edge.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (TF; bit 6 of INTC0). In the pulse width mea-
surement mode with the values of the TON and TE bits
equal to 1, after the TMR has received a transient from
low to high (or high to low if the TE bit is 0 ), it will start
counting until the TMR returns to the original level and
resets the TON. The measured result remains in the
timer/event counter even if the activated transient oc-
curs again. In other words, only 1-cycle measurement
can be made until the TON is set. The cycle measure-
ment will re-function as long as it receives further tran-
sient pulse. In this operation mode, the timer/event
counter begins counting not according to the logic level
but to the transient edges. In the case of counter over-
+ + >
+ >
+ D
0 E
+ D +
0 E
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
(
7
%
( (
Reset Timing Chart
'
9 " $
'
7
<
2
2
A
7
(
+ 7 @
(
2
'
(
Reset Configuration
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