參數(shù)資料
型號(hào)： HT46R62
廠商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 17/46頁(yè)
文件大?。?/td> 401K
代理商： HT46R62
HT46R62/HT46C62
Rev. 1.60
17
July 14, 2005
flows,thecounterisreloadedfromthetimer/eventcoun-
ter register and issues an interrupt request, as in the
other two modes, i.e., event and timer modes.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by in-
structions. The overflow of the Timer/Event Counter is
one of the wake-up sources and can also be applied to a
PFD (Programmable Frequency Divider) output at PA3
by options. Only one PFD can be applied to PA3 by op-
tions . No matter what the operation mode is, writing a 0
to ETI disables the related interrupt service. When the
PFD function is selected, executing SET [PA].3 in-
struction to enable PFD output and executing
CLR
[PA].3 instruction to disable PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR) is read,
the clock is blocked to avoid errors, as this may results
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Timer/Event Counter
Bit No.
Label
Function
0
1
2
PSC0
PSC1
PSC2
To define the prescaler stages.
PSC2, PSC1, PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
TON
Enable/disable timer counting (0=disabled; 1=enabled)
5
Unused bit, read as 0
6
7
TM0
TM1
Defines the operating mode (TM1, TM0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMRC (0EH) Register
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