HT46R46/HT46C46/HT46R47/HT46C47
Rev. 1.00
9
December 28, 2004
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
The memory pointer register MP(01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result 1 . Any writing operation to MPwill only transfer the
lower 7-bit data to MP.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit
ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register
STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-
est-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDFisclearedbyasystempower-uporexecutingthe CLRWDT instruction.PDFissetbyexe-
cuting the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6, 7
Unused bit, read as 0
Status (0AH) Register
" ! 0
%
/
1 1
1
1
1 ,
1
1
1 5
1 6
1 7
1 8
1
1
1
1
1
1 -
1
,
5
6
7
8
-
& !
"
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'
'
'
+
'
B
%
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% C 1 1 C
, -
1
,
*
0
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9 5
$
% :
6 -
1
RAM Mapping for the HT46R47/HT46C47