參數(shù)資料
型號: HT46R22
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit A/D Type MCU
中文描述: 8位A / D型微控制器
文件頁數(shù): 15/46頁
文件大?。?/td> 390K
代理商: HT46R22
HT46R22/HT46C22
Rev. 1.10
15
October 2, 2002
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under soft-
ware control. To function as an input, the corresponding
latch of the control register must write 1 . The input
source also depends on the control register. If the con-
trol register bit is 1 , the input will read the pad state. If
the control register bit is 0 , the contents of the latches
will move to the internal bus. The latter is possible in the
read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H or 18H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 6-bit of port C and 7-bit of port D are
not physically implemented; on reading them a 0 is re-
turned whereas writing then results in a no-operation.
See Application note.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by timer/event
counter overflow signal. The input mode always remain-
ing its original functions. Once the PFD option is se-
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