參數(shù)資料
型號(hào)： HT46R22
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit A/D Type MCU
中文描述： 8位A / D型微控制器
文件頁(yè)數(shù)： 14/46頁(yè)
文件大?。?/td> 390K
代理商： HT46R22
HT46R22/HT46C22
Rev. 1.10
14
October 2, 2002
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller.Thetimer/eventcountercontainsan8-bit
programmablecount-upcounterandtheclockmaycome
from an external source or the system clock.
Using the internal system clock, there is only one refer-
ence time-base. The internal clock source comes from
f
SYS
. Using external clock input allows the user to count
external events, measure time internals or pulse widths,
or generate an accurate time base. While using the in-
ternalclockallowstheusertogenerateanaccuratetime
base.
There are two registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the starting
valuebeplacedinthetimer/eventcounterpreloadregister
and reading TMR gets the contents of the timer/event
counter. The TMRC is a timer/event counter control regis-
ter, which defines some options.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the f
INT
clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the f
INT
.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current con-
tents in the timer/event counter to FFH. Once overflow oc-
curs, the counter is reloaded from the timer/event counter
preload register and generates the interrupt request flag
(TF; bit 5 of INTC) at the same time.
In the pulse width measurement mode with the TON
and TE bits equal to 1, once the TMR has received a
transient from low to high (or high to low if the TE bits is
0 ) it will start counting until the TMR returns to the orig-
inal level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
transientoccursagain.Inotherwords,only1cyclemea-
surement can be done. Until setting the TON, the cycle
measurement will function again as long as it receives
furthertransientpulse.Notethat,inthisoperatingmode,
the timer/event counter starts counting not according to
the logic level but according to the transient edges. In
the case of counter overflows, the counter is reloaded
from the timer/event counter preload register and issues
the interrupt request just like the other two modes. To
enable the counting operation, the timer ON bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is completed. But in
the other two modes the TON can only be reset by in-
structions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ETI can disable the interrupt
service.
In the case of timer/event counter OFF condition, writ-
ing data to the timer/event counter preload register will
alsoreloadthatdatatothetimer/eventcounter.Butifthe
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
Thetimer/eventcounterwillstilloperateuntiloverflowoc-
curs.Whenthetimer/eventcounter(readingTMR)isread,
the clock will be blocked to avoid errors. As clock blocking
mayresultsinacountingerror,thismustbetakenintocon-
sideration by the programmer.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal.
Label
(TMRC)
Bits
Function
PSC0~
PSC2
0~2
To define the prescaler stages, PSC2,
PSC1, PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
TE
3
To define the TMR active edge of
timer/event counter
(0=active on low to high; 1=active on
high to low)
TON
4
To enable or disable timer counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
TM0
TM1
6
7
To define the operating mode
01=Eventcountmode(externalclock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC register
Input/output ports
There are 19 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction MOV
A,[m] (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
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