參數(shù)資料
型號(hào)： HT46C22
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit A/D Type MCU
中文描述： 8位A / D型微控制器
文件頁(yè)數(shù)： 22/46頁(yè)
文件大小： 390K
代理商： HT46C22
HT46R22/HT46C22
Rev. 1.10
22
October 2, 2002
SRW bit
The SRW bit means that the master device wants to
read from or write to the I
2
C BUS. The slave device
check this bit to understand itself if it is a transmitter or a
receiver. The SRW bit is set to 1 means that the mas-
terwantstoreaddatafromtheI
2
CBUS,sotheslavede-
vice must write data to a bus as a transmitter. The SRW
is cleared to 0 means that the master wants to write
data to the I
2
C BUS, so the slave
device must read data from the I
2
C BUS as a receiver.
Acknowledge bit
Oneoftheslavedevicegeneratesanacknowledgesignal,
when the slave address is matched. The master device
can check this acknowledge bit to know if the slave device
accepts the calling address. If no acknowledge bit, the
mastermustsendaSTOPbitandendthecommunication.
When the I
2
C BUS status register bit 6 HAAS is high, it
means the address is matched, so the slave must check
SRW as a transmitter (set HTX) to 1 or as a receiver
(clear HTX) to 0 .
Data byte
The data is 8 bits and is sent after the slave device has
acknowledges the slave address. The first bit is MSB
and the 8th bit is LSB. The receiver sends the acknowl-
edge signal ( 0 ) and continues to receive the next 1
byte data. If the transmitter checks and there s no ac-
knowledge signal, then it release the SDA line, and the
master sends a STOP signal to release the I
2
C BUS.
The data is stored in the HDR register. The transmitter
must write data to the HDR before transmit data and the
receiver must read data from the HDR after receiving
data.
Receive acknowledge bit
When the receiver wants to continue to receive the next
data byte, it generates an acknowledge bit (TXAK) at
the 9th clock. The transmitter checks the acknowledge
bit (RXAK) to continue to write data to the I
2
C BUS or
change to receive mode and dummy read the HDR reg-
ister to release the SDA line and the master sends the
STOP signal.
Stop bit
Start bit
( ( > * (
(
( > !
(
! ! # A
- ' $
( # ) > * (
Data stable and data allow change
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