參數(shù)資料
型號(hào)： HT46C22
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit A/D Type MCU
中文描述： 8位A / D型微控制器
文件頁(yè)數(shù)： 12/46頁(yè)
文件大?。?/td> 390K
代理商： HT46C22
HT46R22/HT46C22
Rev. 1.10
12
October 2, 2002
tions
CLR WDT times selection option . If the CLR
WDT is selected (i.e. CLRWDT times equal 1), any exe-
cution of the CLR WDT instruction will clear the WDT. In
case CLR WDT1 and CLR WDT2 are chosen (i.e.
CLRWDTtimesequaltwo),thesetwoinstructionsmustbe
executedtocleartheWDT;otherwise,theWDTmayreset
the chip because of time-out.
If the WDT time-out period is selected f
s
/2
12
(options), the
WDT time-out period ranges from f
s
/2
12
~f
s
/2
13
, since the
CLR WDT or CLR WDT1 and CLR WDT2 instruc-
tions only clear the last two stages of the WDT.
Power down operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
All of the I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PD flags are ex-
amined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the CLR WDT instruction and is set when executing
the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others keep their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
theinterruptisenabledandthestackisnotfull,theregu-
lar interrupt response takes place. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-upfunctionoftherelatedinterruptwillbedisabled.
Once a wake-up event occurs, it takes 1024 t
SYS
(sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PD and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
SP
Points to the top of the stack
(
* %
5 # & (
- * )
(
Reset timing chart
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