參數(shù)資料
型號(hào)： HT46C22
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit A/D Type MCU
中文描述： 8位A / D型微控制器
文件頁(yè)數(shù)： 10/46頁(yè)
文件大?。?/td> 390K
代理商： HT46C22
HT46R22/HT46C22
Rev. 1.10
10
October 2, 2002
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC0) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC0), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC0),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a sub-
routine call to location 0CH will occur. The related inter-
rupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
Register Bit No. Label
Function
INTC0
(0BH)
0
EMI
Controls the master (global)
interrupt
(1= enabled; 0= disabled)
1
EEI
Controlstheexternalinterrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event
counter interrupt
(1= enabled; 0= disabled)
3
EADI
Controls the A/D converter
interrupt
(1= enabled; 0= disabled)
4
EIF
Externalinterruptrequestflag
(1= active; 0= inactive)
5
TF
Internal timer/event counter
request flag
(1= active; 0= inactive)
6
ADF
A/D converter request flag
(1= active; 0= inactive)
7
Unused bit, read as 0
INTC0 register
The I
2
C BUS interrupt is initialized by setting the I
2
C
BUS interrupt request flag (HIF; bit 4 of INTC1), caused
by a slave address match (HAAS= 1 ) or 1 byte of data
transfer is completed. When the interrupt is enabled, the
stackisnotfullandtheHIFbitisset,asubroutinecalltolo-
cation 10H will occur. The related interrupt request flag
(HIF)willberesetandtheEMIbitclearedtodisablefurther
interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
External Interrupt
1
04H
b
Timer/Event Counter Overflow
2
08H
c
A/D Converter Interrupt
I
2
C BUS Interrupt
3
0CH
d
4
10H
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), A/D converter request
flag (ADF), the I
2
C BUS interrupt request flag (HIF), en-
able timer/event counter bit (ETI), enable external inter-
rupt bit (EEI), enable A/D converter interrupt bit (EADI),
enable I
2
C BUS interrupt bit (EHI) and enable master in-
terrupt bit (EMI) constitute an interrupt control register 0
(INTC0) and an interrupt control register 1 (INTC1)
which are located at 0BH and 1EH in the data memory.
EMI, EEI, ETI, EADI, EHI are used to control the en-
abling/disabling of interrupts. These bits prevent the re-
quested interrupt from being serviced. Once the
interrupt request flags (TF, EIF, ADF, HIF) are set, they
will remain in the INTC0 and INTC1 register until the in-
terrupts are serviced or cleared by a software instruc-
tion.
Register Bit No. Label
Function
INTC1
(1EH)
0
EHI
Controls the I
2
C BUS inter-
rupt(1=enabled;0=disabled)
1
Unused bit, read as 0
2
Unused bit, read as 0
3
Unused bit, read as 0
4
HIF
I
2
C BUS interrupt request
flag (1=active; 0=inactive)
5
Unused bit, read as 0
6
Unused bit, read as 0
7
Unused bit, read as 0
INTC1 register
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