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參數(shù)資料
| 型號(hào)： | HT27LC512 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | OTP CMOS 64Kx 8-Bit EPROM |
| 中文描述： | 檢察官辦公室的CMOS 64Kx 8位存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 258K |
| 代理商： | HT27LC512 |
Functional Description
Operation mode
All the operation modes are shown in the table following.
Mode
CE
OE /VPP
A0
A9
Output
Read
V
IL
V
IL
V
IH
V
IL
V
IH
X
X (2)
X
Dout
Output Disable
X
X
High Z
Standby (TTL)
X
X
High Z
Standby (CMOS)
V
CC
±
0.3V
V
IL
V
IL
V
IH
V
IL
V
IL
X
X
X
High Z
Program
V
PP
V
IL
V
PP
V
IL
V
IL
X
X
D
IN
D
OUT
High Z
Program Verify
X
X
Product Inhibit
X
X
Manufacturer Code (3)
V
IL
V
IH
V
H
(1)
V
H
(1)
1C
Device Code (3)
83
Notes: (1) V
H
= 12.0V
±
0.5V
(2) X=E ither V
IH
or V
IL
(3) For Manufacturer Code and Device Code, A1=V
IH
, When A1=V
IL
, both codes will read 7F
Programming of the HT27LC512
When the HT27LC512 is delivered, the chip has
all 512K bits in the “ONE”, or HIGH state.
“ZE ROs” are loaded into the HT27L C512
through the procedure of programming.
T he programming mode is entered when
12.2
±
0.2V is applied to the OE /VPP pin and CE
is at V
IL
. For programming, the data to be
programmed is applied with 8 bits in parallel to
the data pins.
The programming flowchart in Figure 3. shows
the fast interactive programming algorithm.
The interactive algorithm reduces program-
ming time by using 30
μ
s to 105
μ
s programming
pulses and giving each address only as many
pulses as is necessary in order to reliably pro-
gram the data. After each pulse is applied to a
given address, the data in that address is veri-
fied. If the data is not verified, additional pulses
are given until it is verified or until the maxi-
mum number of pulses is reached. This process
is repeated while sequencing through each ad-
dress of the HT27LC512. This part of the pro-
gramming algorithm is carried at V
CC
=5.8V to
assure that each E PROM bit is programmed to
a sufficiently high threshold voltage. This en-
sures that all bits have sufficient margin. After
the final address is completed, the entire
EPROM memory is read at V
CC
=V
PP
=5.25
±
0.25V
to verify the entire memory.
Program inhibit mode
Programming of multiple HT27LC512 in paral-
lel with different data is also easily accom-
plished by using the Program Inhibit Mode.
Except for CE , all like inputs of the parallel
HT27LC512 may be common. A TTL low-level
program pulse applied to an HT27LC512 CE
input with OE/VPP=12.2
±
0.2V will program that
HT27LC512. A high-level CE input inhibits the
other HT27LC512 from being programmed.
Program verify mode
Verification should be performed on the pro-
grammed bits to determine whether they were
correctly programmed. The verification should
be performed with OE /VPP and CE at V
IL
. Data
should be verified at t
DV
after the falling edge
of CE .
HT27LC512
6
6th May ’99
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