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參數(shù)資料
| 型號： | HSP50215VC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Digital UpConverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, MQFP-100 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 157K |
| 代理商： | HSP50215VC |
3-430
Re-Sampling NCO Application Issues
1. Common clocking of the PUC and PDC:
Note that at a board level, the HSP50214 (PDC) and
HSP50215 (DUC) sample rate NCO’s typically utilize
different clocks. The DUC circuitry is clocked at the master
clock, REFCLK, rate. The PDC output circuitry runs off the
decimated sample rate. If a common sample clock is used
for both parts, then synchronization can be achieved by
scaling and/or truncating the PDC frequency control word to
match the PUC frequency control word. Powers of 2 are
handled by simply truncating the PDC frequency control
word to match the bit width of the DUC frequency control
word. If the PDC decimation factor is not power of 2, then
errors will accumulate.
2. Improving the NCO Accuracy
The Re-Sampler NCO frequency can be adjusted to
maintain phase and frequency lock to a reference clock, if
more accuracy is required.
Interpolation Filter
The Interpolation filter provides sampling rate conversion
from the shaping filter output rate to the final output sample
rate. The nulls in the interpolation filter frequency response
align with the interpolation images of the shaping filter. The
impulse response of the Interpolation filter is shown in
Figures 9A through 9C for an interpolate by 16 filter (the
interpolation ratio, L, is equal to 16). The Interpolation filter
has a pipeline delay of 3 coarse input samples plus 3
REFCLK cycles.
FIGURE 8. RE-SAMPLING NCO BLOCK DIAGRAM
12
30
32
SYNCIN
WR CW3
SAMPLE FREQUENCY
2
ZERO
SHIFTER
IP(1:0)
FINE
PHASE
COARSE
PHASE
SAMPCK
(MSB)
SYNCSEL
EN
ALL REGISTERS ARE
CLOCKED AT REFLCK
4, 3, OR 2
∑
REG
>
REG
>
REG
<
0
M
EnNCO
(CARRIER NCO)
ACC
START
EDGE
GEN
RESET
EDGE
GEN
WR CW21
RST
R
E
G
>
R
E
G
>
FIGURE 9A. INTERPOLATION FILTER IMPULSE RESPONSE
L = 16; FOUT = 4096
FIGURE 9B. INTERPOLATION FILTER IMPULSE RESPONSE
L = 16; FOUT = 4096
FIGURE 9C. INTERPOLATION FILTER IMPULSE RESPONSE
L = 16; FOUT = 4096
0
-20
-40
-60
-80
-100
-120
M
512
1024
1536
SAMPLE TIMES
2048
2560
3072
3584
4096
INTERPOLATION FILTER RESPONSE
0
-20
-40
-60
-80
-100
-120
M
64
128
192
SAMPLE TIMES
256
320
384
448
512
INTERPOLATION FILTER RESPONSE
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
-0.55
-0.6
-0.65
-0.7
M
8
16
24
SAMPLE TIMES
32
40
48
56
64
INTERPOLATION FILTER RESPONSE
HSP50215
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
| HSP50215 | Digital UpConverter(數(shù)字上變頻器) |
| HSP50216 | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
| HSP50307 | Burst QPSK Modulator(混合信號QPSK調制器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50216 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
| HSP50216_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter |
| HSP50216_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
| HSP50216KI | 功能描述:上下轉換器 MULTI-CHANNEL PROGRAMMABLE DOW CONVERTER,BGA PKG,IND TEMP RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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