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參數(shù)資料
| 型號： | HSP50110JC-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CONN HEADER HM 2MM 100POS |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 199K |
| 代理商： | HSP50110JC-52 |
3-249
References
[1] Hogenauer, Eugene, “An Economical Class of Digital
Filters for Decimation and Interpolation”, IEEE
Transactions on Acoustics, Speech and Signal
Processing, Vol. ASSP-29 No. 2, April 1981.
[2] Samueli, Henry “The Design of Multiplierless FIR filters
for Compensating D/A Converter Frequency Response
Distortion”, IEEE Transaction Circuits and Systems,
Vol. 35, No. 8, August 1988.
TABLE 13. PHASE OFFSET REGISTER
DESTINATION ADDRESS = 7
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
Phase Offset
This 8 bit two’s complement value specifies a carrier phase offset of
π
(n/128) where n is the two’s com-
plement value. This provides a range of phase offsets from -
π
to
π
*(127/128). (See Synthesizer/Mixer
Section).
31-8
Reserved.
TABLE 14. TEST REGISTER
DESTINATION ADDRESS = 8
BIT
POSITION
FUNCTION
DESCRIPTION
4-0
Force SPH4-0
When Test Mode enabled*, SPH4-0 is forced to the values programmed in these bit locations. Bit position
4 maps to SPH4. (See Test Mode Section).
5
Force SSTRB
When Test Mode enabled*, SSTRB is forced to state of this bit.
6
Force HI/LO
When Test Mode enabled*, HI/LO is forced to state of this bit.
16-7
Force IOUT9-0
When Test Mode enabled*, IOUT9-0 if forced to the values programmed in these bit locations. Bit position
16 maps to IOUT9.
17
Force DATARDY
When Test Mode enabled*, DATARDY is forced to state of this bit.
18
Force LOTP
When Test Mode enabled*, LOTP is forced to state of this bit.
28-19
Force QOUT9-0
When Test Mode enabled*, QOUT9-0 is forced to the values programmed in these bit locations. Bit posi-
tion 16 maps to QOUT9.
31-29
Reserved.
* Test Mode Enable is Destination Address = 4, bit-3.
TABLE 15. AGC SAMPLE STROBE REGISTER
DESTINATION ADDRESS = 9
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
AGC Read
Writing this address samples the accumulator in the AGC’s Loop Filter. The procedure for reading the
sampled value out of the part on C0-7 is discussed in the Microprocessor Interface Section. (See Micro-
processor Interface Section).
HSP50110
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PDF描述 |
|---|---|
| HSP50110 | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
| HSP50214VI | Programmable Downconverter |
| HSP50214 | Programmable Downconverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110JC-52Z | 功能描述:調(diào)諧器 W/ANNEAL DIGTL TUNER 84 PLCC 52MHZ RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| HSP50110JC-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Tuner Circuit |
| HSP50110JI-52 | 功能描述:調(diào)諧器 DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDUSTRIAL RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
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