參數(shù)資料
型號(hào): HSP45314VI
廠商: INTERSIL CORP
元件分類: 數(shù)字信號(hào)處理外設(shè)
英文描述: CommLinkTM Direct Digital Synthesizer
中文描述: 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP48
封裝: 7 X 7 MM, LQFP-48
文件頁數(shù): 10/14頁
文件大?。?/td> 118K
代理商: HSP45314VI
3-10
Definition of Specifications
Differential Non-Linearity, DNL,
is the measure of the step
size output deviation from code to code. Ideally the step size
should be 1LSB. A DNL specification of 1LSB or less
guarantees monotonicity.
Integral Non-Linearity, INL,
is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Full Scale Gain Drift,
is measured by setting the DAC
inputs to be all logic high (all 1s) and measuring the output
voltage through a known resistance as the temperature is
varied from T
MIN
to T
MAX
. It is defined as the maximum
deviation
from the
value
measured at room temperature to
the
value
measured at either T
MIN
or T
MAX
. The units are
ppm of FSR (Full Scale Range) per
o
C.
Full Scale Gain Error
, is the error from an ideal ratio of 32
between the DAC output current and the full scale adjust
current (through R
SET
).
Internal Reference Voltage Drift,
is defined as the
maximum
deviation
from the
value
measured at room
temperature to the
value
measured at either T
MIN
or T
MAX
.
The units are ppm per
o
C.
Offset Drift,
is measured by setting the DAC inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance as the temperature is varied from T
MIN
to
T
MAX
. It is defined as the maximum
deviation
from the
value
measured at room temperature to the
value
measured at
either T
MIN
or T
MAX
. The units are ppm of FSR (Full Scale
Range) per degree
o
C.
Offset Error,
is measured by setting the DAC inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance. Offset error is defined as the maximum
deviation
of the output current from a value of 0mA.
Output Settling Time,
is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement is done by switching quarter scale.
Termination impedance was 25
due to the parallel
resistance of the 50
loading on the output and the
oscilloscope’s 50
input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Output Voltage Compliance Range,
is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed at either IOUTA or
IOUTB does not violate the compliance range.
Power Supply Rejection,
is measured using a single power
supply. The supply’s nominal +5V is varied
±
10% and the
change in the DAC full scale output current is noted.
Reference Input Multiplying Bandwidth,
is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs to the DAC set to all 1s. The frequency
is increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Spurious Free Dynamic Range, SFDR,
is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
HSP45314
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