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參數(shù)資料
| 型號(hào)： | HSP45314 |
| 廠(chǎng)商： | Intersil Corporation |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | CommLinkTM Direct Digital Synthesizer |
| 中文描述： | CommLinkTM直接數(shù)字頻率合成器 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 118K |
| 代理商： | HSP45314 |
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3-8
TIMING CHARACTERISTICS
Maximum Clock Rate, f
CLK
+5V DV
DD
, +5V AV
DD
(Note 3)
125
-
-
MSPS
Maximum Clock Rate, f
CLK
+3.3V DV
DD
, +5V AV
DD
(Note 3)
100
-
-
MSPS
CLK Pulse Width, t
CW
CLK (Note 3)
5
-
-
ns
Maximum Parallel Write Rate
Rate of WR
50
-
-
MSPS
WR Pulse Width, t
WW
(Note 3)
5
-
-
ns
Data Setup Time, t
DS
Between DATA and WR (Note 3)
10
-
-
ns
Data Hold Time, t
DH
Between DATA and WR (Note 3)
0
-
-
ns
Address Setup Time, t
AS
Between ADDR and WR (Note 3)
12
-
-
ns
Address Hold Time, t
AH
Between ADDR and WR (Note 3)
0
-
-
ns
UPDATE Pulse Width, t
UW
(Note 3)
5
-
-
ns
UPDATE Setup Time, t
US
Between UPDATE and CLK (Note 3)
2
-
-
ns
UPDATE Hold Time, t
UH
Between UPDATE and CLK (Note 3)
4
-
-
ns
UPDATE Latency, t
UL
After UPDATE, before analog output change, if asserted after
writing to the control registers
-
14
-
Clock
Cycles
UPDATE Latency, t
UL
After UPDATE, before analog output change, if asserted before
writing to the control registers
-
11
-
Clock
Cycles
Phase Pulse Width, t
PW
PH(1:0) (Note 3)
5
-
-
ns
Phase Setup Time, t
PS
Between PH(1:0) change and CLK (Note 3)
2
-
-
ns
Phase Hold Time, t
PH
Between PH(1:0) change and CLK (Note 3)
4
-
-
ns
Phase Latency, t
PL
Between PH(1:0) change and analog output change
-
12
-
Clock
Cycles
ENOFR Pulse Width, t
EW
ENOFR (Note 3)
5
-
-
ns
ENOFR Setup Time, t
ES
Between ENOFR and CLK (Note 3)
2
-
-
ns
ENOFR Hold Time, t
EH
Between ENOFR and CLK (Note 3)
4
-
-
ns
ENOFR Latency, t
EL
After ENOFR, before analog output change
-
14
-
Clock
Cycles
Write Enable Pulse Width, t
WR
WE (Note 3)
5
-
-
ns
Write Enable Setup Time, t
WS
Between WE and WR (Note 3)
2
-
-
ns
Write Enable Hold Time, t
WH
Between WE and WR (Note 3)
4
-
-
ns
RESET Pulse Width, t
RW
RESET (Note 3)
5
-
-
ns
RESET Setup Time, t
RS
Between RESET and CLK
-
2
-
ns
RESET Latency to Output, t
RL
After RESET, before analog output reflects reset values
-
11
-
Clock
Cycles
RESET Latency to Write, t
RE
After RESET, before the control registers can be written to
-
1
-
Clock
Cycles
Electrical Specifications
AV
DD
= DV
DD
= +5V (unless otherwise noted), V
REF
= Internal 1.2V, IOUTFS = 20mA,
T
A
= 25
o
C for All Typical Values
(Continued)
PARAMETER
TEST CONDITIONS
HSP45314
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
HSP45314
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相關(guān)代理商/技術(shù)參數(shù) |
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| HSP45314_01 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CommLinkTM Direct Digital Synthesizer |
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| HSP48212 WAF | 制造商:Intersil Corporation 功能描述: |
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