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參數(shù)資料
| 型號(hào)： | HSP45116AVC-52Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 3/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC NCO 52MHZ 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 類型： | 數(shù)控振蕩器（NCO） |
| 頻率： | 52MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 184mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 160-BQFP |
| 包裝： | 托盤 |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 安裝類型： | 表面貼裝 |
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11
FN4156.4
May 7, 2007
through 15 of the NCOM, with the output multiplexers set to
bring out the most significant bits of the CMAC output
(OUTMUX = 00). The most significant 16 bits out of the
PFCS appears on IOUT0-15 and the least significant bits
come out on ROUT0-15.
Complex Multiplier/Accumulator
The CMAC (Figure 1) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations
necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier
and its associated accumulator; the rest of the circuitry
in this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and imaginary inputs RIN and IIN. The two vectors are
combined in the following manner:
ROUT = COS x RIN - SIN x IIN
IOUT = COS x IIN + SIN x RIN
RIN and IIN are latched into the Input Registers and passed
through the shift stages. Clocking of the Input Registers is
enabled with a low on ENI. The amount of shift on the
latched data is programmed with SH0-1 (Table 3). The
output of the shifters is sent to the CMAC and the auxiliary
accumulators.
TABLE 3. INPUT SHIFT SELECTION
SH1
SH0
SELECTED BITS
0
RIN0-15, IMIN0-15
0
1
RIN1-16, IMIN1-16
1
0
RIN2-17, IMIN2-17
1
RIN3-18, IMIN3-18
The 33-bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the Accumulator Section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set of
real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUX0- 1 lines (Table 4). BINFMT controls whether the
output of the Multiplexer is presented in two’s complement or
unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19
for unsigned output, while BINFMT = 1 selects two’s
complement.
TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT
MUX
1
OUT
MUX
0
RO16-19
RO0-15
IO16-19
IO0-15
0
Real CMAC
31-34
Real CMAC
15-30
Imag CMAC
31-34
Imag CMAC
15-30
0
1
Real CMAC
31-34
0, Real
CMAC 0-14
Imag CMAC
31-34
0, Imag
CMAC 0-14
1
0
Real ACC
16-19
Real ACC
0-15
Imag ACC
16-19
Imag ACC
0-15
1
Reserved
The Complex Accumulator duplicates the accumulator in the
CMAC. The input comes from the data shifters, and its 20-bit
complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUX0-1
determines whether the accumulator output appears on
ROUT and IOUT.
The Growth Detect circuitry outputs a two bit value that
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DET0-1, is encoded as
shown in Table 5. If PEAK is low, the highest value of
DET0-1 is latched in the Growth Detect Output Register.
The relative weighting of the bits at the inputs and outputs of
the CMAC is shown in Figure 3. Note that the binary point of
the sine, cosine, RIN and IIN is to the right of the most
significant bit, while the binary point of RO and IO is to the
right of the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOMs for FFT applications.
TABLE 5. GROWTH ENCODING
DET 1
DET 0
NUMBER OF BITS
OF GROWTH ABOVE 2o
0
1
0
2
1
3
HSP45116A
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