參數(shù)資料
型號(hào): HSP-EVAL
廠商: Intersil Corporation
英文描述: DSP Evaluation Platform
中文描述: DSP的評(píng)估平臺(tái)
文件頁數(shù): 1/12頁
文件大?。?/td> 260K
代理商: HSP-EVAL
1
File Number
3366.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
Intersil Corporation 2000
IBM PC is a trademark of IBM Corporation.
HSP-EVAL
DSP Evaluation Platform
The HSP-EVAL is the mother board for a set of daughter
boards based on the HSPxxxxx family of Digital Signal
Processing products. Each product specific daughter board
is mated with the HSP-EVAL to provide a mechanism for
rapid evaluation and prototyping. As shown in Figure 1, the
HSP-EVAL consists of a series of busses which provide
input, output, and control to the target daughter board.
These busses are brought out through dual 96 Pin
connectors to support daisy chaining HSP-EVALs for
multichip prototyping and evaluation.
For added flexibility, the input and control busses can be
driven by registers on-board the HSP-EVAL which have
been down loaded with data via the parallel port of an IBM
PC
TM
or compatible. In addition, a Shift Register is provided
to serialize data on the daughter board output busses for
reading into the PC via the status lines of the parallel port.
Together, the I/O and Control Registers can be used to drive
the target daughter board with a PC based vector set while
collecting daughter board outputs to the PC’s disk.
Jumper selectable clock sources provide three different
methods of clocking the part under evaluation. In mode one,
the clock signal is generated under PC based software
control. In mode two, the HSP-EVALs on-board oscillator may
be selected as the clock source. In mode three, the user may
provide an external clock through the 96 Pin Input Connector.
The HSP-EVAL was built into a 3U Euro-Card form factor
with dual 96 Pin Input/Output connectors. The I/O
connectors conform to the VME J2/P2 connector standard.
Features
Single HSP-EVAL May be Used to Evaluate a Variety of
Parts Within the HSPXXXXX Family of DSP Products
May be Daisy Chained to Support Evaluation of Multi-Chip
Solutions
Parallel Port Interface to Support IBM PC Based
Evaluation and Control
Three Clocking Modes for Flexibility in Performance
Analysis and Prototyping
Dual 96-Pin Input/Output Connectors Conforming to the
VME J2/P2 Connector Standard
Applications
PC Based Performance Analysis of HSPXXXXX Family of
DSP Products
Rapid Prototyping
DSP Evaluation Platform
USER’S MANUAL
May 1999
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