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參數(shù)資料
| 型號： | HS1-82C55ARH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened CMOS Programmable Peripheral Interface |
| 中文描述： | 輻射加固CMOS可編程外設(shè)接口 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大?。?/td> | 165K |
| 代理商： | HS1-82C55ARH |
971
HS-82C55ARH
Pin Description
SYMBOL
PIN
NUMBERS
TYPE
DESCRIPTION
PA0-7
1-4, 37-40
I/O
Port A:
General purpose I/O Port. Data direction and mode is determined by the contents
of the Control Word.
PB0-7
18-25
I/O
Port B:
General purpose I/O port. See Port A.
PC0-3
14-17
I/O
Port C (Lower):
Combination I/O port and control port associated with Port B. See Port A.
PC4-7
10-13
I/O
Port C (Upper):
Combination I/O Port and control port associated with Port A. See Port A.
D0-7
27-34
I/O
Bidirectional Data Bus:
Three-State data bus enabled as an input when CS and WR are
low and as an output when CS and RD are low.
VDD
26
I
VDD:
The +5V power supply pin. A 0.1
μ
F capacitor between pins 26 and 7 is recommend-
ed for decoupling.
GND
7
I
Ground
.
CS
6
I
Chip Select:
A “l(fā)ow” on this input pin enables the communication between the
HS-82C55ARH and the CPU.
RD
5
I
Read:
A “l(fā)ow” on this input pin enables the HS-82C55ARH to send the data or status
information to the CPU on the data bus. In essence, it allows the CPU to “read from” the
HS-82C55ARH.
WR
36
I
W
rite: A “l(fā)ow” on this input pin enables the CPU to write data or control words into the
HS-82C55ARH.
A0 and A1
8, 9
I
Port Select 0 and Port Select 1:
These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the control word registers. They are
normally connected to the Least Significant Bits of the address bus (A0 and A1).
Reset
35
I
Reset:
A “high” on this input clears the control register and all ports (A, B, C) are set to the
input mode. “Bus hold” devices internal to the HS-82C55ARH will hold the I/O port inputs
to a logic “1” state with a maximum hold current of 400
μ
A.
Functional Diagram
GROUP A
CONTROL
POWER
SUPPLIES
DATA
BUS
BUFFER
GROUP B
CONTROL
READ/WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7 - D0
BIDIRECTIONAL
DATA BUS
+5V
GND
8-BIT INTERNAL
DATA BUS
GROUP B
PORT B
(8)
GROUP B
PORT C
LOWER (4)
GROUP A
PORT C
UPPER (4)
GROUP A
PORT A
(8)
I/O
PA7 - PA0
I/O
PC7 - PC4
I/O
PC3 - PC0
I/O
PB7 - PB0
Spec Number
518060
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HS1-82C55ARH-Q | Radiation Hardened CMOS Programmable Peripheral Interface |
| HS1-82C55ARH-8 | Radiation Hardened CMOS Programmable Peripheral Interface |
| HS9-2100RH | Radiation Hardened High Frequency Half Bridge Driver |
| HS-2100RH | Radiation Hardened High Frequency Half Bridge Driver(抗輻射高頻半橋N勾道MOSFET驅(qū)動器) |
| HS9-2100RH-8 | Radiation Hardened High Frequency Half Bridge Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-82C55ARH-8 | 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE PERIPHERAL INTERFACE,DIP,CLS Q - Rail/Tube |
| HS1-82C55ARH-Q | 制造商:Intersil Corporation 功能描述:PERIPHERAL INTRFC 40CDIP - Rail/Tube |
| HS1-82C59ARH-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interrupt Controller |
| HS1-82C85RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Static Clock Controller/Generator |
| HS1-82C85RH-8 | 制造商:Intersil Corporation 功能描述:CLOCK CNTRLR/GENERATOR 24PIN SBDIP - Rail/Tube |
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