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參數(shù)資料
| 型號(hào)： | HS1-82C55ARH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened CMOS Programmable Peripheral Interface |
| 中文描述： | 輻射加固CMOS可編程外設(shè)接口 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 165K |
| 代理商： | HS1-82C55ARH |
986
HS-82C55ARH
CONTROL WORD #12
CONTROL WORD #13
CONTROL WORD #14
CONTROL WORD #15
Mode 0 Configurations
(Continued)
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
0
A
C
B
8
4
4
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
1
A
C
B
8
4
4
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
1
0
A
C
B
8
4
4
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
1
1
A
C
B
8
4
4
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 - D0
Operating Modes
Mode 1 (Strobed Input/Output)
This functional configuration provides a means for transfer-
ring I/O data to or from a specified port in conjunction with
strobes or “handshaking” signals. In Mode 1, Port A and Port
B use the lines on Port C to generate or accept these “hand-
shaking” signals.
Mode 1 Basic Functional Definitions:
Two Groups (Group A and Group B)
Each group contains one 8-bit port and one 4-bit control/
data port.
The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
The 4-bit port is used for control and status of the 8-bit
port.
Input Control Signal Definition
STB (Strobe Input)
A “l(fā)ow” on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgment.
IBF is set by STB input being low and is reset by the rising
edge of the RD input.
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the rising edge of STB and reset by the falling edge of RD.
This procedure allows an input device to request service
from the CPU by simply strobing its data into the port.
INTE A
Controlled by Bit Set/Reset of PC4.
INTE B
Controlled by Bit Set/Reset of PC2.
FIGURE 15. MODE 1 INPUT
INTE
A
PC6, 7
1 = INPUT
0 = OUTPUT
D7 D6 D5 D4 D3 D2 D1 D0
1
CONTROL WORD
MODE 1 (PORT B)
1
1
PA7 - PA0
PC4
PC5
PC3
PC6, 7
RD
8
STB
A
IBF
A
INTR
A
I/O
2
INTE
B
PB7 - PB0
PC2
PC1
PC0
RD
8
STB
B
IBF
B
INTR
B
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
CONTROL WORD
MODE 1 (PORT A)
Spec Number
518060
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HS1-82C55ARH-Q | Radiation Hardened CMOS Programmable Peripheral Interface |
| HS1-82C55ARH-8 | Radiation Hardened CMOS Programmable Peripheral Interface |
| HS9-2100RH | Radiation Hardened High Frequency Half Bridge Driver |
| HS-2100RH | Radiation Hardened High Frequency Half Bridge Driver(抗輻射高頻半橋N勾道MOSFET驅(qū)動(dòng)器) |
| HS9-2100RH-8 | Radiation Hardened High Frequency Half Bridge Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-82C55ARH-8 | 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE PERIPHERAL INTERFACE,DIP,CLS Q - Rail/Tube |
| HS1-82C55ARH-Q | 制造商:Intersil Corporation 功能描述:PERIPHERAL INTRFC 40CDIP - Rail/Tube |
| HS1-82C59ARH-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interrupt Controller |
| HS1-82C85RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Static Clock Controller/Generator |
| HS1-82C85RH-8 | 制造商:Intersil Corporation 功能描述:CLOCK CNTRLR/GENERATOR 24PIN SBDIP - Rail/Tube |
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