參數(shù)資料
型號(hào)： HS1-82C54RH-8
廠商： HARRIS SEMICONDUCTOR
元件分類(lèi)： XO, clock
英文描述： Radiation Hardened CMOS Programmable Interval Timer
中文描述： 3 TIMER(S), PROGRAMMABLE TIMER, CDIP24
文件頁(yè)數(shù)： 19/21頁(yè)
文件大?。?/td> 171K
代理商： HS1-82C54RH-8
966
HS-82C54RH
Operation Common to All Modes
Programming
When a Control Word is written to a Counter, all Control
Logic is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of
CLK. In Modes 0, 2, 3 and 4 the GATE input is level
sensitive, and logic level is sampled on the rising edge of
CLK. In modes 1, 2, 3 and 5 the GATE input is rising-edge
sensitive. In these Modes, a rising edge of Gate (trigger)
sets an edge-sensitive flip-flop in the Counter. This flip-flop is
then sampled on the next rising edge of CLK. The flip-flop is
reset immediately after it is sampled. In this way, a trigger
will be detected no matter when it occurs - a high logic level
does not have to be maintained until the next rising edge of
CLK. Note that in Modes 2 and 3, the GATE input is both
edge-and level-sensitive.
Counter
New counts are loaded and Counters are decremented on
the falling edge of CLK.
The largest possible initial count is 0; this is equivalent to 2
16
for binary counting and 10
4
for BCD counting.
The Counter does not stop when it reaches zero. In Modes
0, 1, 4 and 5 the Counter “wraps around” to the highest
count, either FFFF hex for binary counting or 9999 for BCD
counting, and continues counting. Modes 2 and 3 are
periodic; the Counter reloads itself with the initial count and
continues counting from there.
GATE PIN OPERATIONS SUMMARY
SIGNAL
STATUS
MODES
LOW OR GOING
LOW
RISING
HIGH
0
Disables counting
-
Enables
counting
1
-
1) Initiates count-
ing
2) Resets output
after next clock
-
2
1) Disables counting
2) Sets output imme-
diately high
Initiates counting
Enables
counting
3
1) Disables counting
2) Sets output imme-
diately high
Initiates counting
Enables
counting
4
1) Disables counting
-
Enables
counting
5
-
Initiates counting
-
MINIMUM AND MAXIMUM INITIAL COUNTS
MODE
MIN COUNT
MAX COUNT
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
5
1
0
NOTE: 0 is equivalent to 2
16
for binary counting and 10
4
for BCD
counting.
Spec Number
518059
相關(guān)PDF資料
PDF描述
HS9-82C54RH-8 Radiation Hardened CMOS Programmable Interval Timer
HS1-82C54RH-Q Radiation Hardened CMOS Programmable Interval Timer
HS9-82C54RH-Q Radiation Hardened CMOS Programmable Interval Timer
HS1-82C55ARH Radiation Hardened CMOS Programmable Peripheral Interface
HS1-82C55ARH-Q Radiation Hardened CMOS Programmable Peripheral Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HS1-82C54RH-Q 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBCDIP - Rail/Tube
HS1-82C55ARH 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Radiation Hardened CMOS Programmable Peripheral Interface
HS1-82C55ARH-8 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE PERIPHERAL INTERFACE,DIP,CLS Q - Rail/Tube
HS1-82C55ARH-Q 制造商:Intersil Corporation 功能描述:PERIPHERAL INTRFC 40CDIP - Rail/Tube
HS1-82C59ARH-8 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Interrupt Controller
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