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參數(shù)資料
| 型號： | HS1-82C54RH-8 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | Radiation Hardened CMOS Programmable Interval Timer |
| 中文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, CDIP24 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 171K |
| 代理商： | HS1-82C54RH-8 |
964
HS-82C54RH
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low while OUT is low, OUT is set high immedi-
ately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus
the GATE input can be used to synchronize the
Counter.After writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This allows
the Counter to be synchronized by software also.
Writing a new count while counting does not affect the cur-
rent counting sequence. If a trigger is received after writing a
new count but before the end of the current half-cycle of the
square wave, the Counter will be loaded with the new count
on the next CLK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded at the
end of the current half-cycle.
Mode 3 is implemented as follows:
EVEN COUNTS: OUT is initially high. The initial count is
loaded on one CLK pulse and then is decremented by two
on succeeding CLK pulses. When the count expires, OUT
changes value and the Counter is reloaded with the initial
count. The above process is repeated indefinitely.
ODD COUNTS: OUT is initially high. The initial count is
loaded on one CLK pulse, decremented by one on the next
CLK pulse, and then decremented by two on succeeding
CLK pulses. When the count expires, OUT goes low and the
Counter is reloaded with the initial count. The count is decre-
mented by three on the next CLK pulse, and then by two on
succeeding CLK pulses.When the count expires, OUT goes
high again and the Counter is reloaded with the initial count.
The above process is repeated indefinitely. So for odd
counts, OUT will be high for (N + 1)/2 counts and low for
(N-1)/2 counts.
Mode 4: Software Triggered Mode
OUT will be initially high. When the initial count expires, OUT
will go low for one CLK pulse then go high again.The count-
ing sequence is “Triggered” by writing the initial count.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. This CLK pulse does not
decrement the count, so for an initial count of N, OUT does
not strobe low until N + 1 CLK pulses after the initial count is
written.
If a new count is written during counting, it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte has no effect on counting.
2. Writing the second byte allows the new count to be loaded
on the next CLK pulse.
This allows the sequence to be “retriggered” by software.
OUT strobes low N + 1 CLK pulses after the new count of N
is written.
Mode 5: Hardware Triggered Strobe (Retriggerable)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will
go low for one CLK pulse and then go high again.
After writing the Control Word and initial count, the Counter
will not be loaded until the CLK pulse after a trigger. This
CLK pulse does not decrement the count, so for an initial
count of N, OUT does not strobe low until N + 1 CLK pulses
after trigger.
A trigger results in the Counter being loaded with the initial
count on the next CLK pulse. This allows the counting
sequence to be regretted. OUT strobes low N + 1 CLK
pulses after any new trigger. GATE has no effect on the state
of OUT.
If a new count is written during counting, the current count-
ing sequence will not be affected. If a trigger occurs after the
new count is written but before the current count expires, the
Counter will be loaded with the new count on the next CLK
pulse and counting will continue from there.
NOTES:
1. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
2. The Counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
4. LSB stands for “Least significant byte” of count.
5. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most signifi-
cant byte. Since the Counter is programmed to read/write LSB
only, the most significant byte cannot be read.
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
FIGURE 20. MODE 3
N
N
N
N
0
4
0
2
0
5
0
2
0
4
0
2
0
5
0
2
0
5
0
5
N
N
N
N
0
2
0
4
0
2
0
4
0
4
0
2
CW = 16 LSB = 4
WR
CLK
GATE
OUT
CW = 16 LSB = 5
WR
CLK
OUT
CW = 16 LSB = 4
WR
CLK
GATE
OUT
0
4
0
2
0
4
0
2
N
N
N
N
0
2
0
4
0
2
0
2
0
4
0
2
0
4
0
2
0
4
0
2
Spec Number
518059
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PDF描述 |
|---|---|
| HS9-82C54RH-8 | Radiation Hardened CMOS Programmable Interval Timer |
| HS1-82C54RH-Q | Radiation Hardened CMOS Programmable Interval Timer |
| HS9-82C54RH-Q | Radiation Hardened CMOS Programmable Interval Timer |
| HS1-82C55ARH | Radiation Hardened CMOS Programmable Peripheral Interface |
| HS1-82C55ARH-Q | Radiation Hardened CMOS Programmable Peripheral Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-82C54RH-Q | 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBCDIP - Rail/Tube |
| HS1-82C55ARH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Programmable Peripheral Interface |
| HS1-82C55ARH-8 | 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE PERIPHERAL INTERFACE,DIP,CLS Q - Rail/Tube |
| HS1-82C55ARH-Q | 制造商:Intersil Corporation 功能描述:PERIPHERAL INTRFC 40CDIP - Rail/Tube |
| HS1-82C59ARH-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interrupt Controller |
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