參數(shù)資料
型號(hào): HPC
文件頁(yè)數(shù): 8/30頁(yè)
文件大?。?/td> 361K
代理商: HPC
HPC Core AC Timing Parameters
V
CC
e
5.0V
g
10% (Continued)
Symbol
Description
Ref
Best Case
*
Worst Case
*
Units
FO
e
1
d/FO
FO
e
1
d/FO
MICROWIRE/PLUSDMASTER MODEDFigure 14
tOSKO
C1 to MW Master Clock
C1, RE
6.2
0.4
31.7
2.4
ns
tMWOTM
Master Clock to Data Out (Note 1)
OSKO, FE
6.2
0.4
36.7
2.4
ns
tMWINMs
e
10 ns
Data Setup Time (Note 1)
C1, RE
tMWINMh
e
50 ns
Data Hold Time (Note 1)
C1, RE
MICROWIRE/PLUSDSLAVE MODEDFigure 15
tOSKId
e
1 C2 Cycle
Data Reg. Load to Slave Clock Begin
SIO Load
tMWOTS
Slave Clock to Data Out (Notes 1, 2)
OSKI, FE
6.2
0.4
56.7
2.4
ns
tMWINSs
e
20 ns
Data Setup Time (Note 1)
OSKI, RE
tMWINSh
e
50 ns
Data Hold Time (Note 1)
OSKI, RE
TEST LOGIC MUXES (MUX0–MUX8)DFigure 16
tMUXnlh n
e
0
b
5
Output MUXDUser Mode (Note 1)
1.79
0.11
5.41
0.39
ns
tMUXnhl n
e
0
b
5
Output MUXDUser Mode (Note 1)
1.30
0.13
8.27
0.48
ns
tMUXnlh n
e
6
b
8
Output MUXDUser Mode (Note 1)
0.46
0.07
2.53
0.25
ns
tMUXnhl n
e
6
b
8
Output MUXDUser Mode (Note 1)
0.58
0.07
3.23
0.24
ns
PORT I INPUTS
tI1
e
40 ns Minimum
NMI Pulse Width (Note 1)
tI2
e
40 ns Minimum
I2 Pulse Width (Note 1)
tI3
e
40 ns Minimum
I3 Pulse Width (Note 1)
tI4
e
40 ns Minimum
I4 Pulse Width (Note 1)
Note 1:
This is guaranteed by design and not tested.
Note 2:
Values assume equivalent loading on OSKO, OSKI and MWOT outputs. Actual delay limits will vary due to specific design loading.
Note 3:
Timing includes connection of BF0B4D 4 mA CMOS I/O Buffer to Port A pins.
Best Process, 5.5V,
b
40
§
C.
Worst Case:
Worst Process, 4.5V,
a
100
§
C.
*
Delays are referenced to signal in Ref Column. To relate to CKIN input clock edge, add the appropriate delay from CKIN to the referenced clock (C1, C2).
Best Case:
8
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