參數(shù)資料
型號(hào): HPC
文件頁數(shù): 7/30頁
文件大?。?/td> 361K
代理商: HPC
HPC Core AC Timing Parameters
V
CC
e
5.0V
g
10% (Continued)
Symbol
Description
Ref
Best Case
*
Worst Case
*
Units
FO
e
1
d/FO
FO
e
1
d/FO
HOLD MODEDFigure 10
tNHLDs
e
40 ns
Hold Request Setup Time
C2, FE
tNHLDh
e
50 ns
Hold Request Hold Time
C2, FE
tNHDA
Hold Acknowledge Active
C1, RE
2.4
0.3
12.8
1.6
ns
tPAZ
Port A TRI-STATEs (Note 1, 3)
C1, RE
5.4
0.1
16.2
0.1
ns
SELECT OUTPUTSDFigure 11
tSROM
Address Select Bit
C1, RE
3.9
0.2
20.6
1.1
ns
tSELX
Address Select Bit
C1, RE
3.8
0.2
19.5
1.1
ns
tSELA
Address Select Bit
C1, RE
3.8
0.2
19.5
1.1
ns
tSELB
Address Select Bit
C1, RE
3.8
0.2
19.5
1.1
ns
tSELC
Address Select Bit
C1, RE
3.8
0.2
19.5
1.1
ns
tSELD
Address Select Bit
C1, RE
3.8
0.2
19.5
1.1
ns
tSLIO
Address Select Bit
C1, RE
4.3
0.2
22.7
1.1
ns
WATCHDOGDFigure 12
tWDOT
System Clock to Watch Out (Note 1)
C2, RE
4.1
0.4
21.1
2.4
ns
tSTWDp
e
1 tC2
tWDOTp
e
16tC2
x
32tC2
Set Watchdog Pulse Width (Note 1)
WDOT Pulse Width (Note 1)
TIMERSDINTERNAL CLOCK SOURCEDFigure 13
tT2OT
Clock to Timer 2 Underflow
C2, RE
1.9
0.3
25.8
1.6
ns
tT20Tp
e
1tC1
b
20
Timer 2 Underflow Pulse (Note 1)
tT3OT
Clock to Timer 3 Underflow
C2,RE
1.9
0.3
25.8
1.6
ns
tT30Tp
e
1tC1
b
20
Timer 3 Underflow Pulse (Note 1)
tT0CYp
e
1tC2
b
20
Timer 0 Overflow Pulse (Note 1)
tDIV
Clock to Time Base Generator
C1, RE
2.9
0.3
17.5
1.6
ns
7
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