參數(shù)資料
型號(hào)： HMS91C7432
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： HMS91C7432 features and functions
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 62/90頁(yè)
文件大?。?/td> 1557K
代理商： HMS91C7432
HMS9xC7132 / HMS9xC7134
58
May.2001 ver1.1
18.2 Dynamic PWM
There are two dynamic PWMs in the HMS9xC7132. The DP-
WMs can be used to generate various waveform by software pro-
gramming, and are used to achieve geometric compensation by
generating a parabola output waveform which is synchronized
with VSYNCin signal for pin/trap, bow/tilt, vertical linearity or
focus compensation in monitor system.
This is achieved by utilizing timer2. The low 8-bit in timer2 is
used as 8-bit counter for PWM signal and the high 8-bit in timer2
is used to decide the number of PWMs in one video frame. One
video frame can be divided to any number of blocks according to
the register RC2H value within 256 blocks, and here the RC2L
will be 00H for 8-bit PWM resolution.
The dynamic PWM outputs DPWM0 to DPWM1 register share
the same pins as Port2.0~Port2.1respectively.
The repetition frequency (fDPWM) at a DPWM output is given
by (in case of RC2L=00H): fDPWM = fOSC / (2 x 256)
Table 18-3 Dynamic PWM control register (DPWMCON : 0B1H)
Table 18-4 Description of the DPWMCON bits
Table 18-5 DPWM application circuit
7
6
-
5
-
4
-
3
-
2
-
1
0
DPWMLVL
DPWM1CFG DPWM0CFG
BIT
SYMBOL
FUNCTION
7
DPWMLVL
Polarity selection of the DPWMs.
0 : DPWM outputs are not inverted.
1 : DPWM outputs are inverted.
Output type selection of the DPWMs.
0 : open-drain type.
1 : push-pull type
1 to 0
DPWM1CFG to
DPWM0CFG
DPWMx
Vsync
VDD
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