參數(shù)資料
型號: HMS91C7432
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: HMS91C7432 features and functions
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 49/90頁
文件大?。?/td> 1557K
代理商: HMS91C7432
HMS9xC7132 / HMS9xC7134
May.2001 ver1.1
45
The monitor where HMS9xC7132 resides is always both DDC1
and DDC2 capable with DDC2 having the higher priority. The-
display shall start transmitting DDC1 signals whenever it is pow-
ered on and the vertical sync signal is applied to it from the
hostfor the first time. The display shall switch to DDC2 within 3
system clocks as soon as it sees a high to low transition on the
clockline(SCL), indicating that there are DDC2 devices connect-
ed to the bus. Under that condition, the mode flag, M0 will be
changed from the default setting 0, to 1. Accordingly, the inter-
rupt will be invoked by setting flag, SWHINT as high.
Fig. 16.2 illustrates the concept and interaction between the mon-
itor and the host. After power on, the DDC1EN bit is set by S/W
to act as a DDC1 device. Therefore, the mode flag, M0, is set as
0. Following VSYNC as clock, the monitor will transmit EDID
data stream to the host. However, if DDC2 clock, SCL clock, is
present, the monitor will be switched to DDC2B device with the
mode flag setting as 1. Software will judge it is a DDC2B,
DDC2B+, or DDC2AB protocol.
Figure 16-2 Host type detection
Is VSYNC present
Has a command been received
Is 2B+/A.B command detected
Is monitor DDC2B+/DDC2AB
capable
Is command DDC2B command
Monitor Power on
Communication is idle
EDID sent continuously using
VSYNC as clock
Is DDC2 clock
present
Stop sending of EDID,
Switch to DDC2
communication mode
DDC2 communication
is idle. Monitor is
waiting for a command.
Respond to
DDC2B command
Respond to DDC2B+/
DDC2AB command
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